Asymmetric TFT Patterns for HSD Display Panel Alignment
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Solution Overview
Problem
In large display panels using the half source driving (HSD) structure, the accuracy of metal layer alignment during manufacturing is difficult to control due to thermal expansion and cold shrinkage, leading to variations in gate/drain parasitic capacitance and feed-through voltages between neighboring sub-pixels, which affects display quality.
Innovation Solution
A pixel array design where the orthogonal projection patterns of the thin-film transistors and capacitance electrodes are made substantially the same, ensuring consistent overlay shifts and identical variations in gate/drain parasitic capacitance, thereby maintaining uniform feed-through voltages across sub-pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the HSD structure is used to reduce the number of data lines to half, then the price of the source driver is reduced, but the manufacturing precision of metal layer alignment deteriorates due to thermal expansion and cold shrinkage in large display panels
Solution Approach 1:
The patent applies asymmetry by designing the first and second thin-film transistors with different patterns rather than using traditional symmetric mirror patterns. Specifically, the first thin-film transistor has a gate electrode, channel layer, and source/drain electrodes arranged in a first pattern, while the second thin-film transistor uses a second pattern that is intentionally different. This asymmetric design compensates for overlay variations caused by thermal expansion and cold shrinkage during manufacturing, ensuring that parasitic capacitance variations in both sub-pixels remain substantially the same despite manufacturing tolerances.
2Device complexity
If symmetric mirror patterns are used for thin-film transistors in HSD pixel structure, then the design is simplified, but the display quality deteriorates due to different parasitic capacitances and feed-through voltages in neighboring sub-pixels
Solution Approach 1:
The patent applies local quality by making the transistor patterns locally adapted to compensate for manufacturing variations. Instead of using a uniform symmetric mirror pattern throughout, the first thin-film transistor and second thin-film transistor are designed with different local patterns that are specifically tailored to ensure that their parasitic capacitance variations remain substantially the same. This local differentiation in pattern design allows each transistor to compensate for overlay variations in its specific location, thereby maintaining display quality.
3Area of stationary object
If large display panel size is increased, then the display area is expanded, but the overlay alignment error in each metal layer increases due to thermal expansion and cold shrinkage
Solution Approach 1:
The patent applies asymmetry by designing the first and second thin-film transistors with different patterns rather than using traditional symmetric mirror patterns. Specifically, the first thin-film transistor has a gate electrode, channel layer, and source/drain electrodes arranged in a first pattern, while the second thin-film transistor uses a second pattern that is intentionally different. This asymmetric design compensates for overlay variations caused by thermal expansion and cold shrinkage during manufacturing, ensuring that parasitic capacitance variations in both sub-pixels remain substantially the same despite manufacturing tolerances.
Data Source
AI summary
A pixel array and a display panel are provided. The pixel array includes a plurality of pixel units. Each of the pixel units includes a first scan line, a second scan line, a data line, a first thin-film transistor, a second thin-film transistor, a first pixel electrode and a second pixel electrode. The first thin-film transistor is electrically connected to the first scan line and the data line. The first pixel electrode is electrically connected to the first thin-film transistor. The second thin-film transistor is electrically connected to the second scan line and the data line. The second pixel electrode is electrically connected to the second thin-film transistor. The orthogonal projection pattern of the first thin-film transistor on XY plane and the orthogonal projection pattern of the second thin-film transistor on XY plane are substantially the same.