Solid-State Devices TRIZ Cases

A mechanical debonding system cuts adhesive layers between wafers to separate carrier substrates without chemical immersion.

Calculating the voltage ratio from separate Hall elements eliminates errors caused by vertical looseness and temperature variations in autofocus units.

Chemical oxidation of PbS nanocrystal surfaces modifies lead atom states to eliminate emissive sub-bandgap defects.

A thin film transistor array substrate fabrication method merges multiple contact hole etching steps into a single operation using half-tone or diffractive masks.

Segmented separation dams control inkjet material distribution, reducing volume differences between color filters to prevent surface sag and moire phenomena.

Segmented cathode deposition avoids fine metal masks in transparent regions, reducing image distortion and position errors.

A non-metallic film protects copper metal structures during organic insulating layer formation to ensure reliable electrical contact.

A contact member with multiple faces retains raw material solution droplets on a substrate to define precise film regions during solvent evaporation.

Segmented dams confine functional ink to prevent irregular spreading and ensure uniform film thickness.

Alternating operating and supporting portions with distinct widths prevent bit line bending and word line bridging in 3D stacked memory.

Curved reflector surfaces and substrate troughs minimize chip gaps, converting lateral radiation loss into directed radiant power.

Cross-linked polyorganosiloxane encapsulation resolves moisture barrier and adhesion trade-offs in flexible OLED devices.

An integrated MOS varicap assembly uses parallel segmented capacitors to adjust oscillation frequency characteristics in voltage controlled oscillators.

A collective manufacturing method for light-emitting diodes using substrate bonding and simultaneous contact pad formation.

Segmented acrylic primer blocks gas permeation to silver patterns, resolving trade-offs between light resistance and reliability in LED sealing.

Stepwise program word line voltage and bit line voltage levels selectively control memory cell programming states, reducing overall programming time.

Distributing terminals across opposite substrate surfaces reduces terminal area and module volume while maintaining individual LED control.

An electrode layer masks the sealing film during fluorine-based etching to expose terminals without damaging the organic EL light emitting layer.

A conductive tier with openings accepts an insulator tier to anchor channel material strings in vertically-stacked memory arrays.

A fluorocarbon and helium plasma process deposits a dense protection film on element chip side surfaces to block conductive material spreading.

An organic light receiving layer detects light signals across multiple bands, resolving silicon-based wavelength contrast limitations.

Segmented opening formation and epitaxial growth enable high integration density while reducing manufacturing difficulty and yield loss.

A thin film transistor uses a segmented ohmic conductive film on a light-transmitting semiconductor layer to enable optical inspection of the channel region.

Resistors delay transistor activation to dissipate electrostatic discharge current, reducing layout area compared to complex trigger circuits.

Segmenting the polarizer into hollow and polarizing regions increases screen-to-body ratio while protecting components from damage.

Nonpolar alicyclic polymers suppress ion diffusion and dielectric breakdown, resolving reliability trade-offs in organic semiconductor manufacturing.

Four diodes create a direct current path between differential pins, reducing cross voltage damage from parasitic resistance.

Differentiated liquid crystal cell gaps minimize image stains from kickback voltages while increasing active display area efficiency.

A parallel segmented storage capacitor structure stabilizes current flow in OLED driving circuits.

Segmented transparent substrate isolates micro-LEDs, preventing light mixing and maintaining high display resolution.

Nitridated blocking dielectrics suppress oxidation encroachment to round gate edges, reducing electric field stress and enhancing program-erase endurance.

A light emitting diode package integrates a color filter layer to block unwanted blue wavelengths while transmitting red light output.

Through-holes link adjacent pixel electrodes to repair dark spots from voltage loss while maintaining the display aperture ratio.

A photodiode array merges contact electrodes to remove lateral wiring from the light detecting section.

Segmenting the substrate into a bent third portion with a manufacture sub-portion reduces tensile stress and prevents separation from mechanical members.

Stacked conductive layers in a pixel structure increase storage capacitance without reducing the aperture ratio or display brightness.

Imidazole-fused spiro-cis-stilbene hybrid materials resolve triplet exciton energy loss to boost external quantum efficiency and device lifetime.

A resistor biases the well junction to reduce parasitic capacitance and shorten oscillation start-up time.

Composite partially oxidized metal oxides form p-n heterojunctions that reduce deposition sensitivity and improve device stability.

A light diffusion part on a black layer with an opening directs emitted light to improve orientation characteristics.

Halide exchange patterns metal halide perovskite layers without physical banks, maintaining uniform film thickness and emission wavelength tunability.

A CMOS pixel array uses redundant double row select transistors to segment the row select function and prevent gate shorting.

A pixel array design uses asymmetric thin-film transistor patterns to maintain consistent overlay shifts across sub-pixels.

A coupling capacitor AC couples slider electronics ground to the substrate while DC decoupling it.

A mixed layer and buffer layer structure within an OLED electron transport layer balances electron and hole flow to resolve deposition complexity.

Varying pixel electrode branch widths across regions minimizes texture defects while maintaining manufacturing simplicity.

Recessed channel structures in the memory device minimize electrical deviations and enhance channel strength during miniaturization.

A sub-bit line connects bit lines to page buffer units via a contact unit at a different level above the semiconductor substrate.