Semiconductor Memory Device 3D Stacking Integration
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Solution Overview
Problem
Current semiconductor memory devices face challenges in high integration density due to difficulties in forming openings with large aspect ratios, which affects yield and integration efficiency.
Innovation Solution
The manufacturing method involves forming sacrificial layers and insulating layers in alternating layers, with specific etching processes to create openings and grow semiconductor layers, allowing for high integration without the need for large aspect ratio openings, and using epitaxial growth to form joint semiconductor layers that self-conform positional relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional methods are used to form openings with large aspect ratios for high integration density, then integration density can be improved, but manufacturing difficulty and yield loss increase significantly
Solution Approach 1:
The invention divides the single opening formation process into multiple sequential opening formation steps. First, a first opening is formed through the insulating film to expose the first conductive layer. Then, a second opening is formed through the insulating film to expose the second conductive layer. This segmentation allows each opening to have a smaller, more manageable aspect ratio, avoiding the manufacturing difficulties of forming a single large aspect ratio opening while achieving high integration density through multiple stacked memory cells
Solution Approach 2:
The invention transitions from a planar memory structure to a three-dimensional stacked structure by forming multiple conductive layers (first conductive layer, second conductive layer) stacked in the vertical direction. Memory cells are formed in different height levels, with first memory cells associated with the first conductive layer and second memory cells associated with the second conductive layer. This vertical stacking in another dimension achieves high integration density without requiring large aspect ratio openings
2Quantity of substance
If openings with large aspect ratios are formed to achieve high integration, then integration density improves, but yield loss increases
Solution Approach 1:
The opening formation process is segmented into multiple independent steps, each forming a smaller opening with a manageable aspect ratio. The first opening exposes the first conductive layer, and the second opening exposes the second conductive layer. By segmenting the opening formation, the patent avoids the high yield loss associated with forming a single large aspect ratio opening, while still achieving high integration density through the stacked multi-layer structure
Solution Approach 2:
The patent performs preliminary actions by forming the insulating film and conductive layers in a specific stacked configuration before forming the openings. The insulating film is formed covering both the first and second conductive layers, and the openings are then formed through this pre-prepared structure. This preliminary arrangement of layers enables subsequent opening formation with reduced aspect ratios, improving yield while maintaining integration density
3Ease of manufacture
If conventional opening formation methods are used, then manufacturing process is simpler, but integration density and performance are limited
Solution Approach 1:
The manufacturing process is segmented into distinct, manageable steps: forming the insulating film, forming the first conductive layer, forming the second conductive layer, forming the first opening, and forming the second opening. Each step uses conventional fabrication techniques, maintaining manufacturing simplicity while the cumulative effect of these segmented steps achieves high integration density through vertical stacking
Solution Approach 2:
The patent employs vertical stacking of conductive layers and memory cells in the height direction to achieve high integration density. The first conductive layer and second conductive layer are stacked vertically, with memory cells formed at different height levels. This use of the vertical dimension enables high integration without complicating the manufacturing process, as each layer and opening can be formed using standard sequential fabrication techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high integration density of semiconductor memory devices with reduced yield loss and lower resistance values, improving manufacturing efficiency and device performance.
Implementation Method 1
using epitaxial growth to form joint semiconductor layers that self-conform positional relationships
Data Source
AI summary
A semiconductor memory device includes a first semiconductor layer that includes a first part extending in a first direction, a second part extending in the first direction, and a third part connected to the first and second parts. When a cross-sectional surface extending in second and third directions and including the third part is defined as a first cross-sectional surface, the third part has one side and the other side of an imaginary center line in the third direction in the first cross-sectional surface defined as first and second regions, the third part has maximum widths in the second direction in the first and second regions defined as first and second widths, and the third part has a width in the second direction on the imaginary center line defined as a third width, the third width is smaller than the first and second widths.