Sub-bit Line Contact Structure for NAND Flash Memory
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Solution Overview
Problem
In NAND flash memory devices, the narrow spacing between bit lines leads to challenges in accurately forming electrical contacts, resulting in potential circuit malfunctions due to misaligned or oversized contacts extending across neighboring bit lines.
Innovation Solution
The introduction of a sub-bit line that connects bit lines to page buffer units at a different level above the semiconductor substrate, forming an electrical path through a contact unit to ensure secure and accurate data communication, thereby addressing the contact area issues between bit lines and page buffer units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between bit lines is reduced to increase storage density, then the storage capacity is improved, but the manufacturing precision of contacts deteriorates due to misaligned or oversized contacts extending across neighboring bit lines
Solution Approach 1:
The patent introduces a third dimension by forming the sub-bit line at a different level above the semiconductor substrate than the bit line. This vertical separation allows contacts to be formed at the bit line level without interfering with adjacent bit lines, while the sub-bit line extends to connect to page buffer units at higher levels, thus resolving the contact precision issue while maintaining high storage density
Solution Approach 2:
The sub-bit line acts as an intermediary element between the bit line and the page buffer unit. It provides a dedicated electrical path that separates the contact formation process from the bit line spacing constraints, allowing contacts to be formed accurately at the bit line level while the sub-bit line bridges the connection to page buffer units without requiring precise alignment with tightly spaced bit lines
Data Source
AI summary
A memory device includes; a memory cell array including a memory cell connected to a bit line, a page buffer unit receiving data from the memory cell via the bit line, and a contact unit providing an electrical path through which the data is communicated from the memory cell array to the page buffer unit, wherein the contact unit comprises a sub-bit line configured to connect the bit line via a first contact with the page buffer unit via a second contact.