Semiconductor Memory Device Recessed Channel Structure
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Solution Overview
Problem
Miniaturization of semiconductor memory devices often results in defects in the semiconductor layer, leading to electrical deviations in device characteristics and reduced manufacturing yield, necessitating a structure that minimizes defects to improve reliability.
Innovation Solution
The semiconductor memory device incorporates a conductive layer, first and second electrode layers, semiconductor channel bodies, and insulating layers with recessed portions, where the second semiconductor channel body has a recessed portion on its lateral surface and the second electrode layer has a recessed portion facing the channel body, along with a gate insulating layer formed by thermal oxidation, which helps in reducing crystal defects and enhancing channel body strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor memory device structure is miniaturized, then the device density and integration are improved, but defects are generated in the semiconductor layer resulting in reduced manufacturing yield
Solution Approach 1:
The semiconductor layer is divided into multiple channel bodies (first semiconductor channel body and second semiconductor channel body) with different structural configurations. This segmentation allows each channel body to be optimized independently, reducing the propagation of defects and improving overall manufacturing yield while maintaining high device density.
Solution Approach 2:
Different regions of the semiconductor structure are given different properties: the first semiconductor channel body has a specific crystalline orientation while the second semiconductor channel body has a different crystalline orientation. This local quality differentiation allows optimization for specific functional requirements while reducing defect generation in miniaturized structures.
2Productivity
If the semiconductor layer is miniaturized, then the device characteristics are improved, but electrical deviations are induced in device characteristics such as threshold voltage
Solution Approach 1:
The patent employs asymmetric structural design where the first semiconductor channel body and second semiconductor channel body have different configurations and orientations. This asymmetry compensates for miniaturization-induced variations by creating balanced electrical characteristics across different device regions, thereby reducing threshold voltage deviations.
Solution Approach 2:
The crystalline orientation parameter is changed between different channel bodies (first channel body with one orientation, second channel body with different orientation). This parameter change allows optimization of electrical characteristics to compensate for miniaturization effects, maintaining uniform threshold voltage across the device array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces crystal defects and stress-induced issues, improving the reliability and yield of semiconductor memory devices by minimizing electrical deviations and enhancing the strength of the channel body, thereby supporting the miniaturization process effectively.
Implementation Method 1
a gate insulating layer formed by thermal oxidation
Data Source
AI summary
A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.