Semiconductor Integrated Circuit Parasitic Capacitance Reduction
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Solution Overview
Problem
Semiconductor integrated circuits face challenges in reducing parasitic capacitance between circuit elements and the substrate, which narrows the frequency change range of oscillation circuits and prolongs start-up time due to the influence of parasitic capacitance on electric potential stabilization.
Innovation Solution
A semiconductor integrated circuit design that includes a circuit element formed over a semiconductor substrate with a well of a different conduction type, where a constant voltage biases the junction between the well and the substrate in a reverse direction through a resistor with higher impedance than the reverse-biased junction, reducing parasitic capacitance and shortening start-up time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a well is formed under a capacitor element to reduce parasitic capacitance, then the parasitic capacitance decreases, but the start-up time increases due to slow electric potential stabilization
Solution Approach 1:
A resistor is introduced as an intermediary component connected between the well and ground. This resistor mediates the discharge of the well's electric potential after capacitor charging, enabling controlled potential stabilization that reduces both parasitic capacitance effects and start-up time without direct short-circuiting
Solution Approach 2:
The electric potential of the well is dynamically controlled by applying and removing voltages through the resistor. By changing the voltage state of the well from charged to discharged, the system optimizes both parasitic capacitance reduction during operation and start-up time by enabling rapid potential stabilization
2Adaptability or versatility
If variable capacitors with large capacitance change range are used to achieve wide frequency range, then the frequency change range increases, but the parasitic capacitance narrows the effective capacitance change width
Solution Approach 1:
The parasitic capacitance between the well and substrate, which was previously a harmful factor limiting frequency range, is converted into a beneficial element. By applying voltage to the well, the parasitic capacitance becomes part of the effective capacitance in the oscillation circuit, extending the frequency tuning range rather than limiting it
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces parasitic capacitance and shortens the start-up time of the oscillation circuit, allowing for a wider frequency change range and faster stabilization of oscillation frequency, while maintaining the effect of reducing parasitic capacitance without short-circuiting the well to ground.
Implementation Method 1
a well of a second conduction type different from first conduction type formed in an area of a surface of the semiconductor substrate under the circuit element
Implementation Method 2
parasitic capacitors actually exist between each of the elements and the substrate because all the elements shown in the circuit layout of FIG. 3, except for the quartz oscillator 116, are formed on the same semiconductor substrate
Implementation Method 3
a constant voltage, which biases a junction between the well and the semiconductor substrate in a reverse direction, is applied to the well through a resistor having a higher impedance compared to an impedance of a capacitance of the reverse-biased junction between the well and the substrate at a frequency of a signal applied to the circuit element
Data Source
AI summary
A semiconductor integrated circuit that includes a circuit element with a reduced parasitic capacitance and has a short start-up time. A well of the different type of conduction from that of the substrate is formed in the area of the surface of the semiconductor substrate under the circuit element. A constant voltage, which biases the junction between the well and the semiconductor substrate in a reverse direction, is applied to the well through a resistor having a higher impedance compared with the impedance of the capacitance of the reverse-biased junction between the well and the substrate at the frequency of the signal applied to the circuit element.