Rounded Gate Edge FETs for NAND Flash Endurance
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Solution Overview
Problem
The finite number of program-erase cycles in charge trapping (CT) NAND flash memory devices due to damage of the tunneling dielectric layer during programming and erasing processes limits the endurance of CT-FET memory cells.
Innovation Solution
A fabrication method involving the formation of a tunneling dielectric region, a charge trapping region, and a blocking dielectric region, where the surface of the blocking dielectric region is nitridated to suppress oxidation encroachment into the gate region, resulting in rounded gate edges and consistent dielectric thickness, enhancing program-erase endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Fowler-Nordheim tunneling is used for programming and erasing CT-FET memory cells, then data storage and retrieval functions are achieved, but the tunneling dielectric layer is damaged resulting in finite program-erase cycles
Solution Approach 1:
The gate edges are rounded and the blocking dielectric is nitrided before the tunneling process begins. This preliminary structural preparation creates a more uniform electric field distribution during subsequent program-erase operations, preventing dielectric breakdown at sharp edges and enabling greater numbers of reliable cycles
Solution Approach 2:
The physical geometry of the gate region is changed from sharp edges to rounded edges, and the chemical composition of the blocking dielectric surface is modified through nitridation. These parameter changes create a more durable interface that withstands repeated tunneling stress
2Reliability
If the gate region has sharp edges, then manufacturing is simpler, but electric field stress concentrates at edges causing dielectric damage and reducing endurance
Solution Approach 1:
The gate edges are intentionally rounded rather than kept sharp. This curvature eliminates stress concentration points where electric field intensity would be highest, preventing dielectric breakdown and maintaining structural integrity through repeated program-erase cycles
3Manufacturing precision
If oxidation encroachment occurs during gate region formation, then dielectric coverage is improved, but gate region dimensions are reduced and performance is degraded
Solution Approach 1:
The blocking dielectric surface is nitrided to create a protective layer that resists oxidation encroachment. This preliminary protective action prevents the oxidation process from consuming gate region material, maintaining precise dimensional control and uniform dielectric thickness without requiring complex compensation processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method increases the program-erase endurance and speed of CT-FETs by maintaining consistent dielectric thickness across the gate region, reducing electric field stress and encroachment, thereby improving the performance of flash memory ICs.
Implementation Method 1
The surface of the blocking dielectric region is nitridated
Implementation Method 2
encroachment of the block dielectric region into the gate region is suppressed by the nitridated blocking dielectric region
Implementation Method 3
The gate region is then oxidized, wherein edges of the gate region are rounded
Implementation Method 4
maintaining consistent dielectric thickness across the gate region, reducing electric field stress and encroachment
Data Source
AI summary
Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewalls of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate corners.