Thin Film Transistor Array Substrate Fabrication via Mask Merging
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Solution Overview
Problem
The fabrication of LCD devices with wide viewing angle characteristics, such as IPS and FFS modes, requires additional processes due to the inclusion of a photo acryl layer, increasing the complexity and number of fabrication steps, which needs to be reduced for high-definition and low-power consumption devices.
Innovation Solution
A method for fabricating a thin film transistor array substrate that involves forming a gate electrode and gate line, source/drain electrodes, and a common electrode, with the use of a photo acryl layer and transparent metal layers, utilizing half-tone or diffractive masks to create contact holes and reduce the number of fabrication processes, while maintaining high definition and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a photo acryl layer is formed in FFS mode LCD devices, then power consumption is reduced and load between wires is decreased, but the number of fabrication processes increases
Solution Approach 1:
The patent combines the formation of multiple contact holes (first, second, and third contact holes) into a single fabrication step by simultaneously forming them through one etching process. This merging of operations reduces the total number of fabrication processes while maintaining the low power consumption benefits of the FFS mode structure with photo acryl layer
2Manufacturing precision
If multiple contact holes are formed separately, then each contact hole can be precisely positioned, but the number of fabrication processes increases
Solution Approach 1:
Multiple contact holes at different positions (first contact hole in drain electrode region, second contact hole in gate pad region, third contact hole in data pad region) are formed simultaneously in a single etching step, maintaining precise positioning while reducing process count
Solution Approach 2:
A single mask and etching process serves multiple functions by simultaneously defining multiple contact holes that will connect to different underlying structures (drain electrode, gate pad, data pad), making the process multi-functional rather than requiring separate dedicated processes for each contact hole
Data Source
AI summary
A method of fabricating a thin film transistor array substrate is disclosed. The method includes: sequentially forming a first passivation layer, a photo acryl layer and a first transparent metal layer on the substrate provided with the source/drain electrodes and so on; forming a common electrode, which is disposed in the pixel region, and first through third contact holes, which are positioned in regions of the drain electrode, the gate pad and the data pad, respectively, using one of a half-tone mask and a diffractive mask; forming a second passivation layer on the substrate provided with the first through third contact holes; exposing the drain electrode, the gate pad and the data pad by removing the first and second passivation layers from the drain electrode region, the gate pad region and data pad region; and forming a pixel electrode on the second passivation layer opposite to the common electrode by forming a second transparent metal layer on the substrate and performing a third mask procedure for the second transparent metal layer.