Asymmetric Multi-Layer Wiring Structure for Warpage Reduction
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Solution Overview
Problem
High-end products like flip chip ball grid array (FCBGA) packages for 5G high-speed transmission face issues with warpage and yield reduction due to mismatched coefficients of thermal expansion (CTE) between dielectric and circuit layers in multi-layer substrates, leading to increased thickness and decreased yield.
Innovation Solution
A wiring structure comprising an upper and lower redistribution structure, a conductive structure, and bonding layers to electrically connect and bond these components, with specific thickness ratios and line widths to mitigate thermal expansion mismatches and reduce warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a multi-layer substrate is used to transmit high-speed signals, then signal transmission capability is improved, but warpage occurs due to CTE mismatch between dielectric and circuit layers
Solution Approach 1:
The patent applies asymmetry by making the first and second redistribution structures non-symmetric in configuration, specifically setting different numbers of circuit layers (first redistribution structure has more layers than the second), different dielectric layer arrangements, and different thickness ratios. This asymmetric design balances the overall CTE distribution across the substrate, compensating for thermal expansion mismatches and reducing warpage during thermal processing while maintaining high-speed signal transmission capability.
2Speed
If a multi-layer substrate is used to transmit high-speed signals, then signal transmission capability is improved, but thickness increases
Solution Approach 1:
The patent applies local quality by optimizing the thickness distribution of dielectric and circuit layers in different regions of the substrate. Specifically, the first dielectric structure has a different thickness ratio compared to the second dielectric structure (within 0.58 to 3), and the circuit layers are strategically positioned with varying thicknesses. This localized optimization reduces the overall substrate thickness while maintaining the necessary signal transmission performance through targeted layer configurations.
3Speed
If a multi-layer substrate is used to transmit high-speed signals, then signal transmission capability is improved, but yield decreases
Solution Approach 1:
The patent applies preliminary action by pre-balancing the CTE and thickness parameters during the substrate design phase. The first and second redistribution structures are configured with specific thickness ratios (dielectric layers: 0.58 to 3, circuit layers: 0.3 to 3) before manufacturing and thermal processing. This preliminary optimization of structural parameters prevents warpage and manufacturing defects from occurring, thereby improving substrate yield while enabling high-speed signal transmission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure significantly reduces warpage during thermal processing and improves yield by balancing thermal expansion and thickness, enhancing the reliability and efficiency of high-speed signal transmission.
Implementation Method 1
The upper bonding layer is disposed between the upper redistribution structure and the conductive structure to bond the upper redistribution structure and the conductive structure together. The lower bonding layer is disposed between the lower redistribution structure and the conductive structure to bond the lower redistribution structure and the conductive structure together.
Implementation Method 2
The conductive structure is disposed between and electrically connected to the upper redistribution structure and the lower redistribution structure.
Data Source
AI summary
A wiring structure is provided. The wiring structure includes an upper redistribution structure, a lower redistribution structure, a conductive structure, an upper bonding layer and a lower bonding layer. The conductive structure is disposed between and electrically connected to the upper redistribution structure and the lower redistribution structure. The upper bonding layer is disposed between the upper redistribution structure and the conductive structure to bond the upper redistribution structure and the conductive structure together. The lower bonding layer is disposed between the lower redistribution structure and the conductive structure to bond the lower redistribution structure and the conductive structure together.