Asymmetrical Electrolytic Plating for Thin Metal Vias
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Solution Overview
Problem
Existing methods for producing electrically conductive vias in microelectric circuits are inefficient due to the time-consuming nature of electroless plating and the requirement for a catalytic layer, as well as the inability to effectively deposit thin metal walls along the sides of via holes using electrolytic plating.
Innovation Solution
Asymmetrical electrolytic plating is employed, where one surface of a dielectric substrate is coated with a conductive material and the opposite surface is not, allowing metal deposition to start at the bottom of channels and grow vertically along the sides using electrolytic plating, with the use of plating and etching resist materials to control the deposition process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If electroless plating is used to deposit metal in via holes, then metal deposition can occur without a conductive surface, but the process takes excessively long time and requires a catalytic layer
Solution Approach 1:
The patent extracts and removes the catalytic layer step from the conventional electroless plating process. By using electrolytic plating instead, metal deposition is achieved directly on conductive surfaces without requiring autocatalytic reactions or preliminary catalytic coating, thereby eliminating the time-consuming steps while maintaining metal deposition capability
Solution Approach 2:
The patent substitutes the chemical autocatalytic mechanism of electroless plating with the electrical field-driven mechanism of electrolytic plating. This replacement uses electrical current to drive metal ion deposition, achieving faster deposition rates and eliminating the need for catalytic layers while maintaining effective metal filling capability
2Productivity
If electrolytic plating is used to deposit metal in via holes, then deposition is faster and no catalytic layer is needed, but thin metal walls along the sides of via holes cannot be effectively produced
Solution Approach 1:
The patent applies local quality by creating asymmetric conductivity distribution within the via hole structure. The inner walls are coated with conductive material to serve as localized cathodes, while the bottom remains non-conductive. This localized conductivity difference directs the electrolytic plating current to deposit metal preferentially on the side walls, enabling precise formation of thin metal walls while maintaining high deposition speed
Solution Approach 2:
The patent introduces a vertical dimension to conductivity distribution within the via hole. By coating only the side walls with conductive material and leaving the bottom non-conductive, the patent creates a three-dimensional conductivity gradient that controls the deposition pattern, enabling metal to be deposited vertically along the walls rather than uniformly filling the hole
3Ease of manufacture
If conventional electrolytic plating is used with coated walls and bottom of via holes, then metal can be deposited, but an extra step is required to make the thin metal layer along the walls
Solution Approach 1:
The patent extracts and removes the unnecessary step of coating the via hole bottom with conductive material. By leaving the bottom non-conductive and only coating the side walls, the patent simplifies the process to a single electrolytic plating step that automatically produces the desired thin metal wall structure without requiring additional masking or selective deposition steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the efficient production of electrically conducting vias with thin metal walls along the sides of channels, reducing processing time and eliminating the need for a catalytic layer, while ensuring uniform metal deposition.
Implementation Method 1
The substrate, along with the electrical conductor layer and one or more channels, is placed in an electrically conducting bath in the presence of voltage differential between an anode and the electrical conductor (acting as a cathode). This causes metal from an anode to be deposited onto the electrical conductor by electrolytic plating.
Implementation Method 2
placed in an electrically conducting bath in the presence of voltage differential between an anode and the electrical conductor (acting as a cathode)
Data Source
AI summary
The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.