Asymmetrical Memory Core Structure to Suppress GIDL Writing Errors

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In three-dimensional semiconductor memory devices, the potential difference in the semiconductor layer during writing operations leads to a high risk of erroneous writing due to GIDL current, which causes electron injection and potential gradient issues.

Innovation Solution

The semiconductor memory device is designed with a varying width of the semiconductor layer and core insulating layer, where the width of the semiconductor layer in certain regions is made larger than in others to reduce the potential gradient and minimize electron injection, thereby reducing the risk of erroneous writing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a three-dimensional semiconductor memory device is designed with uniform width semiconductor layer, then manufacturing is simplified, but potential gradient and electron injection increase causing erroneous writing

Engineering Contradiction:
Improvewriting accuracyVSAvoidsemiconductor layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by varying the width of the semiconductor layer in different regions. Specifically, the semiconductor layer has a first width in a first region and a second width in a second region, where the widths differ to create different potential gradients in different areas. This local variation suppresses electron injection and potential gradient issues that cause erroneous writing, while maintaining overall device functionality.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs asymmetry by designing the semiconductor layer with non-uniform width across different regions. The asymmetric width configuration creates different electrical characteristics in different regions, which helps to control and suppress the potential gradient and electron injection that lead to writing errors, thereby improving writing accuracy without requiring complete structural redesign.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If the semiconductor layer width is varied to suppress GIDL current, then writing accuracy improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improvewriting accuracyVSAvoidlayer width control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by modifying the width parameter of the semiconductor layer in different regions. By changing the width parameter from a uniform value to varied values (first width in first region, second width in second region), the patent suppresses GIDL current and improves writing accuracy. This parameter variation is designed to be implementable with standard manufacturing tolerances.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively suppresses the generation of GIDL current, thereby reducing the likelihood of erroneous writing and enhancing the reliability of data storage operations.

Implementation Method 1

the potential difference in the semiconductor layer during writing operations leads to a high risk of erroneous writing due to GIDL current, which causes electron injection and potential gradient issues

Methodology Applied
Scientific EffectPotential gradient: Electric Field

Implementation Method 2

the potential difference in the semiconductor layer during writing operations leads to a high risk of erroneous writing due to GIDL current

Methodology Applied
Scientific EffectGIDL current: Electrical Resistance

Data Source

PatentUS12550321B2Semiconductor memory device including an asymmetrical memory core region
Publication Date: 2026.02.10 KIOXIA CORP
  • US12550321B2 patent drawing
  • US12550321B2 patent drawing
  • US12550321B2 patent drawing

AI summary

According to embodiments, a semiconductor memory device includes a plurality of control gate electrodes laminated above a substrate and extend in a first direction and a second direction, and a memory pillar that has one end connected to the substrate, has longitudinally a third direction intersecting with the first direction and the second direction, and is opposed to the plurality of control gate electrodes. The memory pillar includes a core insulating layer and a semiconductor layer arranged around the core insulating layer. The semiconductor layer includes a first portion and a second portion positioned at a substrate side of the first portion. A width in the first direction or the second direction of the semiconductor layer at at least a part of the first portion is larger than a width in the first direction or the second direction of the second portion.