Asynchronous Circuit Replication for Single-Event Fault Blocking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Asynchronous electronic circuits are vulnerable to transient faults, particularly single-event effects (SEEs) and single-event upsets (SEUs) caused by radiation, which can lead to deadlocks and incorrect data computation, and existing fault-tolerant solutions are not applicable to asynchronous circuits.

Innovation Solution

The design of fault-tolerant asynchronous circuits involves replicating signals and gates, using series transistors and C-elements to create independent nodes, and implementing staticizer circuits to prevent state changes during faults, ensuring that only one replica is affected by a single event, allowing the circuit to wait for agreement before proceeding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If asynchronous circuits are used without clock signals, then circuit speed and flexibility are improved, but vulnerability to transient faults and radiation effects increases

Engineering Contradiction:
Improvecircuit operation speedVSAvoidfault tolerance
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The circuit is segmented into multiple independent signal paths (dual-rail encoding with p and n signals). Each path operates independently to detect and handle transient faults, allowing the circuit to maintain asynchronous speed while improving reliability through distributed fault detection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Feedback mechanisms are implemented where circuit outputs are monitored and fed back to detect glitches and transient faults. The feedback paths enable the circuit to identify erroneous states caused by radiation effects and correct them, maintaining reliability without sacrificing asynchronous operation speed.

Inventive Principle:
Principle #23Feedback

2Reliability

If replication of signals and gates is implemented, then fault tolerance is improved, but device complexity increases

Engineering Contradiction:
Improvefault toleranceVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Signal replication is implemented using dual-rail encoding where each logical signal is copied into two physical signals (p and n). This copying approach provides fault tolerance by allowing glitch detection through comparison, while the replication structure follows systematic patterns that manage complexity through regularity rather than arbitrary complexity.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The replicated signal structure serves multiple functions simultaneously: it provides fault detection, glitch filtering, and logical operation capability. This multi-functionality reduces the need for separate dedicated fault-tolerance components, thereby managing overall device complexity while maintaining high reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If staticizer circuits with multiple C-elements are used, then immunity to single-event effects is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvesingle-event effect immunityVSAvoidcircuit fabrication complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The staticizer circuit uses C-elements with specific timing parameters and signal levels designed to detect single-event effects. By carefully selecting and controlling electrical parameters such as signal thresholds and timing windows, the circuit achieves high immunity to single-event effects while maintaining compatibility with standard manufacturing processes.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The staticizer circuit performs preliminary detection and correction of single-event effects before they can propagate through the circuit. By placing detection logic at strategic points and using pre-configured C-element structures, the circuit prepares for and handles radiation effects proactively, reducing the need for complex post-detection correction mechanisms.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7505304B2Fault tolerant asynchronous circuits
Publication Date: 2009.03.17 ACHRONIX SEMICONDUCTOR CORP
  • US7505304B2 patent drawing
  • US7505304B2 patent drawing
  • US7505304B2 patent drawing

AI summary

New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.