Asynchronous Communication Circuit With Acknowledgment Pause for SEU Recovery
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Solution Overview
Problem
Asynchronous circuits in avionics and space applications are vulnerable to radiation-induced single event faults (SEUs), leading to circuit malfunctions and processing delays, with existing redundancy techniques either lacking error correction or increasing power and area consumption significantly.
Innovation Solution
An asynchronous circuit design incorporating a comparator to detect mismatches between data signals, an acknowledgment pause circuit to prevent signal propagation during errors, and a non-volatile memory circuit to store and provide data values, allowing for error correction without resetting the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If double modular redundancy (DMR) is used to protect against radiation, then reliability is improved, but error correction capability is lost and circuit complexity increases
Solution Approach 1:
The circuit is divided into two functionally equivalent redundant circuits that operate in parallel. Each circuit processes data independently, and their outputs are compared to detect errors. This segmentation allows error detection while maintaining simpler individual circuit units compared to full TMR implementation.
Solution Approach 2:
A comparator circuit acts as an intermediary between the two redundant circuits. It compares the outputs of both circuits and generates an error signal when mismatches are detected. This intermediary component enables error detection without requiring the full complexity of triple modular redundancy.
2Reliability
If triple modular redundancy (TMR) is used to protect against radiation, then reliability and error correction are improved, but circuit area and power consumption increase by a factor of three
Solution Approach 1:
Instead of implementing three full redundant circuits as in TMR, the patent segments the redundancy into two circuits with a shared comparator. This reduces the overall circuit area and power consumption while maintaining error detection and correction capabilities through the comparison mechanism.
Solution Approach 2:
The patent merges the error detection function into a separate comparator circuit that serves both redundant circuits. This allows two circuits to provide redundancy benefits without requiring the full three-circuit TMR structure, thereby reducing power consumption and area while maintaining reliability.
3Reliability
If triple modular redundancy (TMR) is used to protect against radiation, then reliability and error correction are improved, but circuit area increases by a factor of three
Solution Approach 1:
The redundancy is segmented into two separate but functionally equivalent circuits rather than three, reducing the total circuit area. The comparator circuit provides the error detection function without requiring a third full redundant circuit, thus reducing area while maintaining radiation resistance.
Solution Approach 2:
The comparator circuit serves as a universal component that enables error detection for both redundant circuits. This multi-functional approach allows the system to achieve TMR-like error correction capabilities with fewer physical circuits, thereby reducing overall area consumption.
4Reliability
If DMR is used to detect errors, then reliability is improved, but processing delay increases due to reset requirements
Solution Approach 1:
The comparator provides continuous feedback by comparing the outputs of the two redundant circuits in real-time. When an error is detected, the feedback signal triggers the acknowledgment pause circuit to prevent propagation of erroneous data. This continuous feedback mechanism enables error detection without requiring circuit reset, thereby reducing processing delays.
Solution Approach 2:
The acknowledgment pause circuit is designed to preemptively pause acknowledgment signal propagation when errors are detected, before the error can cause further processing issues. This preliminary action prevents the need for subsequent reset operations, reducing overall processing delay while maintaining reliability.
Data Source
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Figure 6~8A
AI summary
The invention relates to an asynchronous circuit which comprises: a first circuit (404) suitable for receiving, from a first other circuit, a first data input signal, and for generating a first acknowledgement of receipt signal and a first data output signal; a second circuit (404') suitable for receiving, from a second other circuit, a second data input signal, and for generating a second acknowledgement of receipt signal and a second data output signal, the second circuit being functionally equivalent to the first circuit; a comparator (414) suitable for detecting an inconsistency between the first and second data input or output signals; and at least one circuit for pausing an acknowledgement of receipt suitable for preventing the propagation of the first and second acknowledgement of receipt signals towards the first and second other circuits if an inconsistency is detected by the comparator.