Asynchronous Clock Domain Adapter for NoC Power Disconnect
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Solution Overview
Problem
Conventional network-on-chip (NoC) designs face challenges in data transfer between asynchronous clock domains and power management, leading to potential data loss or instability when power is disconnected, and difficulties in clock tree insertion and power rail routing due to separate clock and power domains.
Innovation Solution
A power disconnect module is introduced that includes an asynchronous clock domain adapter unit between the master and slave side managers, allowing for physical separation of these units and enabling localized operation within single clock and power domains, with an optional bypass path for synchronous mode to minimize latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If separate clock domains are used to allow different frequencies for different parts of the network, then timing closure becomes easier and power consumption is reduced, but data transfer between clock domains becomes complex and requires additional components
Solution Approach 1:
An asynchronous clock domain adapter is introduced as an intermediary component between the first clock domain logic and the second clock domain logic. The adapter includes a sender in the first clock domain that writes data to a buffer and a receiver in the second clock domain that reads data from the buffer, enabling correct data transfer between asynchronous clock domains without requiring complex synchronization protocols
2Device complexity
If the asynchronous clock domain adapter sender and receiver are placed in the same power domain, then power management is simplified, but data loss or instability occurs when power is disconnected
Solution Approach 1:
The asynchronous clock domain adapter is segmented into separate sender and receiver portions that can be placed in different power domains. The sender is associated with a first power domain and the receiver with a second power domain, allowing independent power management of each portion while maintaining data integrity through the buffer-based architecture
Solution Approach 2:
The buffer is pre-configured with write and read pointers that track the position of data elements. Before power disconnection occurs, the sender can continue writing to the buffer and the receiver can continue reading, ensuring that data transfer completes successfully even when power domains are independently managed
3Length of stationary object
If clock tree insertion is performed across significant distances on the chip, then global clock distribution is achieved, but timing closure becomes difficult and power rail routing complexity increases
Solution Approach 1:
The clock distribution system is segmented into multiple independent clock domains, each with its own local clock source. Logic units are assigned to specific clock domains and operate with localized clocks, eliminating the need for long-distance clock tree insertion and balancing while reducing power rail routing complexity
Solution Approach 2:
The asynchronous clock domain adapter acts as an intermediary that connects logic units operating in different localized clock domains. This allows each clock domain to be independently optimized with short clock trees while still enabling communication across the entire chip through the adapter's buffer mechanism
Data Source
AI summary
A power disconnect unit within a data transport topology of a NoC includes an asynchronous clock domain adapter unit inserted between a master side manager unit and a slave side manager unit. This configuration allows for the master and slave side managers of the power disconnect unit to be placed physically far apart on the chip, relieving the need to route long power rail signals on the chip. A response data path and associated asynchronous clock domain adapter unit is optionally included on the chip. A path to bypass the asynchronous clock domain adapter units is optionally included on the chip to enable a fully synchronous mode of operation without the data latency cost of the asynchronous adapter unit.