Asynchronous Clock Data Acquisition for Stable DPD Alignment

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Solution Overview

Problem

Existing digital pre-distortion technologies for power amplifiers are limited to cases where clock domains of downlink and feedback data are the same, restricting their application range and increasing calculation complexity and inaccuracies in wireless communication systems.

Innovation Solution

A data acquisition method that performs anti-jitter processing on storage flags to synchronize and align data acquisition clocks, ensuring consistent delays between asynchronous clock domains, thereby expanding the application range and simplifying calculations in digital pre-distortion processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If digital pre-distortion technology is used to cancel nonlinear distortion caused by power amplifier, then efficiency of power amplifier is improved, but application range is limited to cases where clock domains of downlink data and feedback data are same

Engineering Contradiction:
Improveefficiency of power amplifierVSAvoidapplication range
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent introduces a clock domain conversion mechanism as an intermediary between downlink data and feedback data with different clock domains. This mediator enables data acquisition from asynchronous clock domains while maintaining the digital pre-distortion functionality, thereby expanding application range without sacrificing amplifier efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If data acquisition is performed with asynchronous clock domains, then application range is expanded, but calculation complexity and inaccuracies increase

Engineering Contradiction:
Improveapplication rangeVSAvoidcalculation complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary clock domain conversion and data alignment before the digital pre-distortion calculation process. By pre-synchronizing the data from asynchronous clock domains, the system avoids complex calculations during the main processing stage, thereby reducing calculation complexity and improving accuracy while maintaining expanded application range.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If data acquisition is performed with asynchronous clock domains, then application range is expanded, but measurement precision and accuracy decrease

Engineering Contradiction:
Improveapplication rangeVSAvoidaccuracy of data acquisition
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent introduces a clock domain conversion mechanism as an intermediary between downlink data and feedback data with different clock domains. This mediator enables data acquisition from asynchronous clock domains while maintaining the digital pre-distortion functionality, thereby expanding application range without sacrificing amplifier efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent performs preliminary clock domain conversion and data alignment before the digital pre-distortion calculation process. By pre-synchronizing the data from asynchronous clock domains, the system avoids complex calculations during the main processing stage, thereby reducing calculation complexity and improving accuracy while maintaining expanded application range.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4075668B1Data acquisition method, apparatus and device, and storage medium
Publication Date: 2025.12.31 SANECHIPS TECH CO LTD
  • EP4075668B1 patent drawingFigure 1~2
  • EP4075668B1 patent drawingFigure 3
  • EP4075668B1 patent drawingFigure 4

AI summary

The present application provides a data acquisition method, a data acquisition apparatus, a data acquisition device and a storage medium. The data acquisition method includes: obtaining a first storage flag, the first storage flag is configured to indicate a flag bit at which first data starts to be acquired and stored; when a first data acquisition clock is asynchronous with a second data acquisition clock, obtaining a second storage flag according to the first data acquisition clock and the second data acquisition clock, the second storage flag is a storage flag bit corresponding to the first storage flag after the first storage flag crosses from the first data acquisition clock to the second data acquisition clock; and performing anti-jitter processing on the second storage flag to obtain a third storage flag, and acquiring second data according to the third storage flag, a delay between the first data and the second data acquired each time is kept unchanged.