Asynchronous Clock Retiming Using Fractional Phase Edge Selection
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Solution Overview
Problem
Asynchronous clock retiming methods using a series of registers introduce metastability conditions, leading to timing uncertainty and increased probability of errors, which are unacceptable in certain applications.
Innovation Solution
The method involves using a time-to-digital converter to determine the fractional phase error between asynchronous clocks and selecting the edge of the higher frequency clock that is farthest from the lower frequency timing signal, ensuring minimal metastability by resampling the reference clock with both edges of the oversampling clock and choosing the edge with greater separation, thereby avoiding timing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a series of registers are used to retiming a lower frequency clock by a higher frequency clock, then the retiming function is achieved, but the probability of metastability condition increases exponentially with each register stage
Solution Approach 1:
The patent measures the time interval between the lower frequency clock edge and the higher frequency clock edges in advance, before selecting which edge to use for retiming. This preliminary measurement allows the system to proactively avoid metastability conditions by choosing the optimal sampling edge based on predicted timing relationships, rather than reactively dealing with metastability after it occurs.
Solution Approach 2:
The patent implements a feedback mechanism where the measured time interval is used to control the selection of the higher frequency clock edge for retiming. The system continuously monitors the timing relationship and adjusts its edge selection accordingly, creating a closed-loop control system that dynamically optimizes retiming to minimize metastability probability while maintaining reliability.
2Reliability
If multiple register stages are used to achieve acceptable MTBF rate, then reliability improves, but timing uncertainty increases due to metastability resolving at different clock periods
Solution Approach 1:
The patent performs preliminary measurement of the time interval between clock edges before the retiming operation. By knowing the exact timing relationship in advance, the system can select a higher frequency clock edge that guarantees adequate setup and hold times, thereby eliminating timing uncertainty that would otherwise arise from metastability resolution at different clock periods.
Solution Approach 2:
The measured time interval feeds back into the edge selection logic, creating a controlled retiming process where the output timing is deterministically determined by the measurement. This feedback mechanism ensures that the retimed signal maintains precise timing relationships with the original lower frequency clock, preventing timing errors while achieving acceptable MTBF rates.
3Reliability
If the number of registers is reduced to decrease device complexity, then the metastability probability increases, but if increased to improve reliability, the device complexity and cost increase
Solution Approach 1:
The patent introduces a time interval measurement mechanism as an intermediary between the lower frequency clock and the higher frequency clock registration process. This intermediary provides critical timing information that enables intelligent edge selection, allowing the system to achieve high reliability with fewer register stages by making informed decisions about which clock edges to sample, thereby reducing the exponential growth of metastability probability.
Solution Approach 2:
The patent changes the operational parameters of the retiming process by dynamically selecting different higher frequency clock edges based on measured timing relationships. Instead of using a fixed number of register stages with fixed timing characteristics, the system adapts its sampling parameters (which clock edge to use) based on real-time measurements, enabling reliable retiming with reduced device complexity.
Data Source
AI summary
A time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of the lower frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two registers: one on the rising edge and the other on the falling edge. Then, the register of “better quality” retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output.