Asynchronous Clock Domain Data Transfer Synchronization
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Solution Overview
Problem
Existing testing and diagnostic equipment is not designed to validate or emulate fully asynchronous architectures, as it relies on deterministic synchronous models, making it difficult to record and reproduce conditions and events in systems with multiple asynchronous clock domains.
Innovation Solution
A system that generates a synchronization signal synchronously with one clock domain to allow data transfer and correlation between asynchronous clock domains, using reporting logic to indicate the number of clock cycles in the second domain during synchronization periods, enabling validation and emulation of asynchronous interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If synchronous protocols are used for data transfer, then deterministic validation and testing are enabled, but the system cannot support multiple asynchronous clock domains efficiently
Solution Approach 1:
The patent introduces an intermediary mechanism that captures and stores clock cycle information from asynchronous clock domains during synchronization events. This intermediary storage allows the deterministic testing equipment to record and later reproduce asynchronous behavior, bridging the gap between asynchronous operation and synchronous validation requirements
Solution Approach 2:
The system performs preliminary capture of clock cycle counts and synchronization event information before validation is needed. By pre-recording the asynchronous timing relationships in storage, the system enables subsequent deterministic reproduction and validation without requiring the actual asynchronous conditions to be present during testing
2Reliability
If all clock domains are synchronized, then deterministic testing is possible, but engineering costs and power consumption increase significantly
Solution Approach 1:
The patent extracts only the essential timing information (clock cycle counts and synchronization events) from the asynchronous clock domains rather than forcing full synchronization. This extraction approach maintains the asynchronous operational benefits while capturing sufficient data for deterministic validation, significantly reducing power consumption compared to full synchronization
3Use of energy by stationary object
If asynchronous clock domains are used, then power consumption and engineering costs are reduced, but validation and emulation become difficult
Solution Approach 1:
The system creates a deterministic copy of the asynchronous timing behavior by recording clock cycle counts and synchronization events in storage. This copy can be later reproduced by the testing equipment, allowing full validation and emulation of asynchronous interactions without requiring the actual asynchronous hardware to be present during testing, thus reducing validation difficulty
Data Source
AI summary
Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.