Generating/Distributing Signals TRIZ Cases
- Asynchronous Clock Domain Data Transfer Synchronization
Reporting logic records clock cycle counts to validate asynchronous architectures.
- Dual-Clock Time Management for Automation Equipment
A dual-clock system combines a hardware real-time clock with a software millisecond counter to manage time in automation equipment.
- Clock Dithering for Power Budget Management
Cycling between two clock generators adjusts the average frequency to keep power consumption within budget limits during high computational loads.
- Modular Retimer Elements for PCIe Link Width Scaling
Segmented retimer elements synchronize via wired-OR signals and serial buses to form scalable link widths.
- Wearable Clock Synchronization via Rate Correction
A wearable device corrects external timestamps using internal clock rate changes.
- Dual Buffer Clock Domain Data Transfer Latency
Two specialized buffers and a multiplexor resolve latency trade-offs in variable frequency clock domain transfers.
- Partial Clock Gating in Network-on-Chip SoC
A network-on-chip architecture uses a clock gating control module to selectively deliver clock signals to IP blocks.
- FSM Clock Switching Circuit for Asynchronous Signal Synchronization
Finite state machine manages clock switching between oscillators to provide synchronized primary and enable signals.
- DDR Reference Voltage Training Using Clock Recovery
A DDR reference voltage training scheme uses a clock recovery loop to position the sampling point for optimal signal integrity.
- Multimode Clock Generation Circuit for Microprocessors
A multimode clock generation circuit produces pulse and phase signals via a single unified path, eliminating clock skew from dual generators.