FSM Clock Switching Circuit for Asynchronous Signal Synchronization
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Solution Overview
Problem
Embedded systems, such as SoCs and MCUs, face challenges in synchronizing clock signals across different clock frequencies generated by various oscillators, leading to signal timing glitches and latency issues during clock switching.
Innovation Solution
A clock switching circuit and finite state machine (FSM) are used to manage clock frequencies, providing an uplink primary clock signal and enable signal to IPs, allowing them to generate internal clocks based on received signals, thereby mitigating glitches and reducing latency by synchronizing clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock switching is performed between different oscillators, then clock frequency adaptability is improved, but signal timing glitches occur during switching
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the second clock signal to the first clock signal before switching occurs. The clock management circuit receives the second clock signal from a different oscillator, synchronizes it to the first clock signal's timing, and then switches to the synchronized signal, preventing timing glitches during the transition.
Solution Approach 2:
The patent uses an intermediary approach by introducing a clock management circuit that acts as a mediator between different oscillators. This circuit synchronizes clock signals from different sources before they are used by circuit units, ensuring smooth transitions without timing glitches.
2Speed
If clock switching is performed rapidly, then response time to frequency requests is improved, but latency issues occur during switching
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the second clock signal to the first clock signal before switching occurs. The clock management circuit receives the second clock signal from a different oscillator, synchronizes it to the first clock signal's timing, and then switches to the synchronized signal, preventing timing glitches during the transition.
Solution Approach 2:
The patent uses feedback mechanisms where the clock management circuit continuously monitors clock frequency requests from circuit units and adjusts clock signal selection accordingly. The synchronous sampling of enable signals provides feedback to ensure proper timing alignment during transitions.
3Adaptability or versatility
If multiple clock frequencies are provided to different IPs, then operational flexibility is improved, but synchronization complexity increases
Solution Approach 1:
The patent applies merging by combining multiple clock signals into a unified synchronized output. The clock management circuit receives clock signals from multiple oscillators, synchronizes them to a common reference (first clock signal), and provides a single synchronized clock output to circuit units, reducing synchronization complexity.
Solution Approach 2:
The patent applies universality by designing the clock management circuit to handle multiple clock sources and frequency requirements through a single unified interface. The circuit can provide different clock frequencies to different IPs while maintaining synchronization through the common first clock signal reference.
Data Source
AI summary
Aspects of the disclosure provide for an apparatus. In an example, the apparatus includes a clock switching circuit coupled to oscillators and one or more circuit units. The clock switching circuit is configured to receive, from the oscillators, a set of frequency signals, provide an uplink primary clock signal and an enable signal to the one or more circuit units, the enable signal determined synchronously with the uplink primary clock signal, receive, from the one or more circuit units or a clock management circuit, a clock frequency request, provide the uplink primary clock signal based on a first signal of the set of frequency signals, and according to the clock frequency request, determining whether to continue to provide the uplink primary clock signal based on the first signal or on a second signal of the set of frequency signals.