Clock Dithering for Power Budget Management
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Solution Overview
Problem
Selecting an optimum clock frequency for a processing unit is challenging due to interdependent factors like voltage, current, temperature, and power consumption, especially in AI/machine learning applications, where power budgets need to be managed to prevent excessive power draw during computationally intensive phases.
Innovation Solution
A method involving cycling between two clock generators with different frequencies, adjusting the proportion of time spent on each to maintain an average frequency that balances performance and power consumption, using a comparator to monitor current and switch between generators based on power budget thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to improve processing performance, then the application executes more rapidly, but the power consumption increases and may exceed the power budget
Solution Approach 1:
The system implements periodic switching between two clock generators with different frequencies. The first clock generator operates at a higher frequency during periods when power budget allows, while the second operates at a lower frequency when power constraints are approached. This periodic alternation enables the system to achieve high average processing speed while maintaining average power consumption within budget limits.
Solution Approach 2:
The system dynamically adjusts the clock frequency by selecting between two different clock generators based on real-time power consumption conditions. The switching is controlled by monitoring power usage and adapting the clock frequency accordingly, allowing the system to optimize the balance between performance and power consumption during application execution.
2Use of energy by moving object
If the clock frequency is decreased to reduce power consumption, then the power budget is maintained, but the processing performance decreases
Solution Approach 1:
Instead of maintaining a constantly low clock frequency, the system uses periodic switching between low and high frequency modes. The lower frequency clock generator is activated during high-power consumption periods to stay within budget, while the higher frequency generator is used during lower-power periods to maintain overall processing throughput and application performance.
3Device complexity
If a single clock generator is used to simplify the system, then the device complexity is reduced, but the ability to dynamically manage power and performance is limited
Solution Approach 1:
The system employs two clock generators that serve multiple functions: the first clock generator provides high-frequency operation for performance-critical periods, while the second provides low-frequency operation for power-constrained periods. Both generators receive the same reference clock signal and can be selectively activated based on power consumption conditions, making the clock system universally adaptable to varying performance and power requirements.
Data Source
AI summary
A system and method for docking a processing unit provided. According to the method, the system dithers between the two signals provided by the two clock generators so as to clock the processing unit at an average clock frequency having a value between the frequencies of the two signals. The average clock frequency is adjusted by modifying the proportion of time spent on one clock signal vs the other clock signal.