Modular Retimer Elements for PCIe Link Width Scaling
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Solution Overview
Problem
PCIe links have limited length due to high speeds and material properties, requiring multiple retimer devices for different lane widths, leading to inventory issues, heat dissipation challenges, and complex signal routing in space-constrained applications.
Innovation Solution
Developing retimer elements that can be combined to form varying widths, using a wired-OR signal for synchronization and a serial bus for state information transfer to maintain synchronous operation, reducing the number of parts needed and simplifying heat dissipation and signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple retimer devices with different lane widths are used, then the PCIe link can support various data throughput requirements, but inventory complexity increases
Solution Approach 1:
The retimer device is divided into multiple independent retimer elements that can be configured in series to support different lane widths. Each element handles a subset of lanes, allowing flexible combination to match various PCIe link requirements without needing separate devices for each width.
Solution Approach 2:
A single retimer element design serves multiple functions by being configurable to handle different numbers of lanes when combined with other elements. The same basic element can be used in 1-lane, 2-lane, 4-lane, or 8-lane configurations, eliminating the need for dedicated retimer devices for each width.
2Productivity
If wider retimer devices are used for higher lane widths, then more data throughput is achieved, but heat dissipation becomes more difficult
Solution Approach 1:
The retimer functionality is segmented across multiple independent elements distributed on the circuit board. Each element generates heat locally but can be thermally managed independently through distributed heat sinks or cooling structures, reducing the thermal density problem of monolithic wide retimers.
Solution Approach 2:
Instead of concentrating all retimer functionality in a single wide device, the elements are distributed across the circuit board in a spatial dimension. This distribution allows heat to be dissipated across a larger area rather than concentrated in one location.
3Productivity
If wider retimer devices are used for higher lane widths, then more data throughput is achieved, but the space required increases
Solution Approach 1:
The retimer is segmented into multiple smaller elements that can be arranged in series along the signal path. This modular arrangement achieves the same functional throughput capability as a wide retimer but with a more compact overall footprint, as elements share infrastructure and can be positioned close together.
Solution Approach 2:
The retimer elements are arranged in a series configuration along the signal transmission path rather than in parallel within a single wide device. This longitudinal arrangement reduces the lateral footprint while maintaining the necessary lane width capability through sequential processing of signals.
4Adaptability or versatility
If more signals are routed to and from the retimer device, then more lanes are supported, but the printed circuit board becomes more complicated
Solution Approach 1:
The signal routing is segmented into multiple independent paths, each connecting to a separate retimer element. This modular routing approach simplifies the overall PCB design compared to a monolithic device, as each element can be connected using standardized patterns and the routing can be distributed across different regions of the board.
Solution Approach 2:
Each retimer element handles only a subset of lanes (partial action), which simplifies the routing requirements for each individual element connection. The cumulative effect of multiple elements provides the full lane width capability without requiring all signals to be routed through a single complex interface.
Data Source
AI summary
Differing widths of retimers are developed using differing numbers of individual retimer elements combined together. To maintain synchronous operation, various signals are provided between the individual retimer elements to allow synchronization of the various operations. A first signal is a wired-OR signal that is used for event and operation synchronization. A second set of signals form a serial bus used to transfer proper state information and operation correction data from a master retimer element to slave timer elements. The combination of the wired-OR signal and the serial bus allow the various state machines and operations inside each retimer element to be synchronized, so that the entire width of the link is properly synchronized.