Partial Clock Gating in Network-on-Chip SoC
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Solution Overview
Problem
As the demand for integration and high performance of System on Chip (SoC) increases, there is a need for effective power management techniques to reduce power consumption, particularly in reducing dynamic power consumption without redesigning existing Intellectual Property (IP) blocks.
Innovation Solution
The implementation of a low power SoC that supports partial clock gating through a network on chip architecture, which includes clock gate circuits and a clock gating control module to selectively deliver or block clock signals to IP blocks based on request, allowing for dynamic power reduction without altering the existing IP design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration and number of IP blocks in SoC is increased to meet demand for integration and high performance, then system functionality and performance are improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock gating control where the clock signal delivery to IP blocks is adjusted in real-time based on their operational state. The clock gating control module dynamically switches between delivering and blocking clock signals to different IP blocks, enabling the system to adapt power consumption to actual operational needs rather than maintaining static power supply to all blocks.
Solution Approach 2:
The patent applies selective clock gating to specific IP blocks based on their individual operational requirements. Instead of uniformly managing power across the entire SoC, the system independently controls clock delivery to each IP block through separate clock gating control, allowing localized power optimization without affecting other functional blocks.
2Use of energy by moving object
If clock gating is implemented to reduce dynamic power consumption, then power usage is reduced, but device complexity increases due to additional control circuits
Solution Approach 1:
The clock gating control module serves multiple functions: it receives clock gating control signals from various IP blocks, determines whether to deliver or block clock signals, and manages the timing of these operations. This multi-functional design consolidates what could be multiple separate control circuits into a single unified module, reducing overall complexity while maintaining comprehensive clock gating capability across all IP blocks.
Solution Approach 2:
The patent combines the clock gating control functionality for multiple IP blocks into a single centralized clock gating control module. Instead of implementing separate clock gating circuits for each IP block, the system merges these functions into one module that can manage clock delivery to multiple blocks, thereby reducing the total number of control circuits and simplifying the overall device architecture.
3Use of energy by moving object
If existing IP blocks are modified to support clock gating, then power control capability is improved, but design cost and development time increase
Solution Approach 1:
The clock gating control module acts as an intermediary between IP blocks and the clock distribution network. Rather than requiring modifications to the IP blocks themselves, this intermediary module intercepts clock gating control signals from IP blocks and manages the actual clock signal delivery. This approach allows existing IP blocks to maintain their original design while still enabling fine-grained power control through the intermediary clock gating mechanism.
Solution Approach 2:
The patent segments the clock control function from the IP block functionality. By separating the clock gating control logic into an independent module rather than integrating it within each IP block, the system allows existing IP blocks to remain unchanged while still achieving power control. This segmentation enables reuse of existing IP designs without requiring redesign, thereby reducing design costs and development time.
Data Source
AI summary
A low power system on chip for supporting partial clock gating is provided. The system on chip includes a network on chip including a first CG-network interface module, a second CG-network interface module, and a clock gating control module, a first IP block that communicates through the first CG-network interface module, and a second IP block that communicates through the second CG-network interface module. The clock gating control module receives a clock gating request from the first IP block, outputs a communication control signal to the second CG-network interface module in response to the received clock gating request, and performs a clock gating operation for a clock signal in response to the received clock gating request to selectively deliver the clock signal to the second IP block.