DDR Reference Voltage Training Using Clock Recovery
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Solution Overview
Problem
Conventional reference voltage training schemes for DDR interfaces, such as GDDR6, face challenges in maintaining optimal timing and voltage noise margins due to system voltage temperature drift, requiring periodic or continuous training that disrupts operations.
Innovation Solution
A VREF training scheme that utilizes a clock recovery loop to position the clock at an optimal sampling point, adjusting the reference voltage based on in-phase and quadrature-phase samples to minimize timing loss and improve voltage noise margin, allowing training during maintenance mode without halting operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional VREF training schemes perform eye-scan at initialization, then optimal VREF value and DQS delay can be determined, but VREF training must be paused during maintenance mode to compensate for voltage temperature drift
Solution Approach 1:
The patent performs VREF training and DQS delay optimization in advance during initialization mode before normal operations begin. This preliminary action establishes optimal parameters that can withstand voltage temperature drift during maintenance mode, eliminating the need to pause operations for re-training.
Solution Approach 2:
The patent introduces a dynamic switching mechanism between initialization mode and maintenance mode. The system dynamically adjusts its operational state based on whether re-training is needed, allowing seamless transition without pausing data operations during maintenance mode while still maintaining optimal performance.
2Reliability
If VREF training is performed periodically or continuously during maintenance mode, then voltage temperature drift compensation is achieved, but READ operations must be halted to perform eye-scan
Solution Approach 1:
The patent performs VREF training and DQS delay optimization in advance during initialization mode before normal operations begin. This preliminary action establishes optimal parameters that can withstand voltage temperature drift during maintenance mode, eliminating the need to pause operations for re-training.
Solution Approach 2:
The patent enables continuous data operations to proceed without interruption by completing all necessary VREF training and parameter optimization during initialization mode. The system maintains optimal performance through continuous operation rather than periodic interruptions for re-training.
3Measurement precision
If brute-force eye-scan is used to obtain READ PASS/FAIL plot, then maximum eye opening provides optimal VREF and DQS delay values, but the process is time-consuming and requires operation pause
Solution Approach 1:
The patent performs VREF training and DQS delay optimization in advance during initialization mode before normal operations begin. This preliminary action establishes optimal parameters that can withstand voltage temperature drift during maintenance mode, eliminating the need to pause operations for re-training.
Solution Approach 2:
The patent introduces a dynamic switching mechanism between initialization mode and maintenance mode. The system dynamically adjusts its operational state based on whether re-training is needed, allowing seamless transition without pausing data operations during maintenance mode while still maintaining optimal performance.
Data Source
AI summary
Various aspects of the subject technology relate to systems, methods, and machine-readable media for DDR reference voltage training. The method includes receiving a data stream, the data stream including pulses generated from a reference voltage in relation to a voltage input logic low and a voltage input logic high of an input stream. The method also includes receiving a clock signal, the clock signal including an in-phase signal and a quadrature-phase signal, the in-phase signal orthogonal to the quadrature-phase signal. The method also includes utilizing the in-phase signal and the quadrature-phase signal of the clock signal in relation to the data stream to obtain a stream of in-phase samples and a stream of quadrature-phase samples. The method also includes adjusting the reference voltage based on a relationship of the stream of in-phase samples to the stream of quadrature-phase samples.