Asynchronous Switching Converter State Machine Without Clock Overhead
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Solution Overview
Problem
Existing finite state machines for switching converters face issues with high power consumption and incompatibility with digital circuits due to synchronous and asynchronous implementations, and GALS-type state machines are slow and limited by metastability resolution times.
Innovation Solution
An asynchronous finite state machine implemented using D flip-flops and combinational circuits without dedicated asynchronous components, where transitions are controlled by D flip-flops and combinational circuits, reducing the need for state registers and local clock signals, and optimizing power consumption and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a synchronous finite state machine is used, then the state machine can be implemented with standard digital circuit components, but the power consumption is high and the clock frequency must be much greater than the switching frequency
Solution Approach 1:
The patent applies dynamic operation by making the state machine asynchronous, where state transitions occur based on event triggers rather than a fixed clock cycle. This allows the circuit to operate only when state changes are needed, significantly reducing power consumption compared to synchronous operation where the clock continuously drives the circuit.
Solution Approach 2:
The patent eliminates periodic clock action entirely by using event-driven transitions. Instead of a continuous periodic clock signal that drives all flip-flops every cycle, the system transitions states only when specific conditions are met, removing the need for high-frequency periodic operation and reducing power consumption.
2Use of energy by moving object
If a purely asynchronous finite state machine is used, then power consumption is reduced, but the design requires dedicated asynchronous components and development tools that are incompatible with standard digital circuit tools
Solution Approach 1:
The patent segments the asynchronous operation into individual event-triggered transitions rather than requiring a fully asynchronous design. Each state transition is independently controlled by specific trigger conditions, allowing the use of standard digital components while achieving asynchronous behavior. This segmentation enables compatibility with conventional digital circuit design tools.
Solution Approach 2:
The patent uses combinational logic circuits as intermediaries between the asynchronous event triggers and the synchronous flip-flops. These intermediary circuits process the trigger conditions and generate appropriate transition signals, bridging the gap between asynchronous operation requirements and synchronous component implementation, thus maintaining compatibility with standard digital tools.
3Ease of manufacture
If a GALS-type state machine is used, then compatibility with digital circuits is maintained, but the machine is slow and limited by metastability resolution times
Solution Approach 1:
The patent applies preliminary action by evaluating all transition conditions in combinational logic before triggering any state changes. The combinational circuits pre-process the trigger signals and determine the next state in advance, eliminating the need for metastability resolution and allowing faster transitions compared to GALS approaches that must wait for clock synchronization.
Solution Approach 2:
The patent extracts the clock synchronization requirement entirely from the state machine operation. By removing the dependency on clock edges and metastability resolution, the system achieves faster operation while maintaining compatibility with digital circuits through the use of standard flip-flops triggered by asynchronous events rather than periodic clocks.
4Device complexity
If a synchronous finite state machine is used, then the circuit can be implemented with state registers and combinational circuits, but the clock frequency must be much greater than the switching frequency which increases power consumption
Solution Approach 1:
The patent makes the state machine dynamic and event-driven, where the operational frequency adapts to the actual switching requirements rather than being constrained by a fixed high-frequency clock. This dynamic operation maintains the simplicity of state register implementation while dramatically improving efficiency by operating only when needed.
Data Source
AI summary
An asynchronous finite state machine has states coupled by transitions each implemented by a flip-flop. Each flip-flop supplies a bit of a state of arrival of the corresponding transition, and receives a bit of an initial state of this transition on its data input and a first signal dedicated to the flip-flop on its control input. A circuit supplies, for each transition, a second signal of request for the transition. Another circuit generates based on the second signals, at each request for a transition and in the absence of a pulse of the first signals, a pulse of the first signal dedicated to the flip-flop of this transition, and a pulse of the first signal dedicated to each flip-flop supplying a bit to the flip-flop of the transition.