Asynchronous Finite State Machines Using Virtual Clock Events
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Solution Overview
Problem
Existing asynchronous finite state machines (FSMs) lack compatibility with existing resources, making it difficult to leverage the benefits of asynchronous implementation while overcoming limitations such as resource overhead and challenges in automatic test pattern generation.
Innovation Solution
The system includes an asynchronous finite state machine configured to transition between states in response to virtual-clock events, a trigger circuit that asserts a trigger signal based on asynchronous event signals, and a virtual clock-pulse circuit that generates virtual-clock events from the trigger signal, allowing the FSM to manage state transitions akin to synchronous FSMs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If asynchronous finite state machines are implemented using traditional asynchronous designs, then speed and power consumption are improved, but compatibility with existing resources and design tools deteriorates
Solution Approach 1:
The patent introduces a virtual clock signal as an intermediary between the asynchronous FSM and existing synchronous design resources. The virtual clock is generated internally based on state transitions and is used to control the timing of internal logic operations, allowing the asynchronous FSM to interface with synchronous components and tools while maintaining asynchronous operation characteristics for speed and power benefits
Solution Approach 2:
The virtual clock mechanism enables the asynchronous FSM to serve multiple functions: it operates asynchronously for efficient event-driven processing while simultaneously providing synchronous-like timing signals that are compatible with standard design tools and existing synchronous resources, making the system universally applicable
2Quantity of substance
If asynchronous finite state machines use event-driven transitions without virtual clocks, then resource overhead is reduced, but compatibility with standard design tools and testing procedures deteriorates
Solution Approach 1:
The patent applies partial synchronization by introducing a virtual clock only where needed for interfacing with synchronous tools and resources, while the core FSM operation remains asynchronous and event-driven. This partial application of synchronous timing provides enough compatibility for standard design tools without fully converting the system to synchronous operation, thus maintaining resource efficiency
3Adaptability or versatility
If virtual-clock events are used to trigger state transitions, then compatibility with synchronous FSMs is improved, but device complexity increases
Solution Approach 1:
The virtual clock signal is generated self-service by the asynchronous FSM itself based on its own state transitions. The FSM monitors its state changes and automatically generates appropriate virtual clock pulses, eliminating the need for external clock generation circuitry and reducing overall system complexity while maintaining compatibility with synchronous interfaces
Data Source
AI summary
A system including an asynchronous finite state machine that transitions from a first state to a second state in response to receiving a virtual-clock event signal. The system further includes a trigger circuit that asserts a trigger signal when a first-state asynchronous event signal is asserted while the asynchronous finite state machine is in the first state. The system further including a virtual clock-pulse circuit configured to generate the virtual-clock event signal after receiving the trigger signal.