Asynchronous Full-Adder Majority Gates for Low-Voltage Carry Logic
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Solution Overview
Problem
Existing asynchronous logic circuits using stacks of transistors between power supply rail and ground rail face challenges in low voltage conditions, making it difficult to implement full-adders effectively.
Innovation Solution
Implement asynchronous full-adders using majority and minority gates with capacitive input circuits, utilizing linear or nonlinear dielectric capacitors such as ferroelectric or paraelectric materials, which reduce the stack of devices and enable operation at lower power supply levels, allowing for area reduction and higher throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional stacks of transistors are used in asynchronous logic circuits, then the circuit can be implemented with conventional components, but the circuit cannot operate effectively in low voltage conditions and requires larger area
Solution Approach 1:
The patent changes the fundamental operating parameters of the logic circuit by replacing transistor-based switching with capacitive switching using linear or nonlinear dielectric materials. This parameter change enables the circuit to operate at lower voltages (1V or less) while reducing the area required for implementation, as the capacitive structure requires fewer series devices between power supply rails compared to traditional transistor stacks.
Solution Approach 2:
The patent employs composite material structures, specifically using linear dielectric or nonlinear dielectric (ferroelectric or paraelectric) materials in the capacitive input circuits. These materials enable the circuit to achieve both low-voltage operation and area reduction by providing the necessary electrical characteristics without requiring deep transistor stacks, thus resolving the contradiction between operating voltage and circuit area.
2Productivity
If traditional asynchronous logic with transistor stacks is used, then the implementation is straightforward with conventional components, but the throughput is limited and area efficiency is reduced
Solution Approach 1:
By changing from transistor-based to capacitive-based logic operation, the patent achieves higher throughput per unit area. The capacitive switching mechanism allows for faster operation and better area utilization, directly improving the productivity parameter while reducing the area footprint compared to traditional asynchronous logic implementations.
3Adaptability or versatility
If stacks of transistors greater than 4 transistors are used, then full-adder functionality can be achieved, but the circuit becomes difficult to use in low voltage conditions
Solution Approach 1:
The patent substitutes the mechanical/electronic transistor switching mechanism with a capacitive field-based switching mechanism. This substitution eliminates the need for deep transistor stacks, reducing device complexity while improving voltage adaptability. The capacitive input circuit responds to voltage changes through electric field effects rather than requiring sequential transistor switching, enabling operation at lower voltages with simpler device structures.
Solution Approach 2:
The use of linear or nonlinear dielectric materials in the capacitive structure provides the necessary electrical characteristics to achieve full-adder functionality without deep transistor stacks. These materials enable the circuit to maintain proper logic levels and switching behavior at lower voltages, thus improving voltage adaptability while reducing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables asynchronous circuits to operate at lower voltages, reducing area by 3× and increasing throughput by 2× compared to traditional asynchronous circuits, while also allowing operation in synchronous circuits.
Implementation Method 1
The capacitive input circuit includes a first linear or nonlinear dielectric capacitor having a first terminal coupled to the first input and a second terminal coupled to a summing node
Implementation Method 2
utilizing linear or nonlinear dielectric capacitors such as ferroelectric or paraelectric materials
Implementation Method 3
utilizing linear or nonlinear dielectric capacitors such as ferroelectric or paraelectric materials
Data Source
AI summary
Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and/or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.