Asynchronous Full-Adder Using Majority Gates for Low-Voltage Logic
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Solution Overview
Problem
Existing asynchronous logic circuits using stacks of transistors face challenges in low voltage conditions, particularly below 1V, making it difficult to implement a full-adder efficiently.
Innovation Solution
Asynchronous circuits utilizing majority and minority gates with capacitive input circuits, incorporating linear or nonlinear dielectric capacitors, reduce the stack of devices between supply and ground, allowing operation at lower voltages and reducing area and increasing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional stacks of transistors are used in asynchronous logic circuits, then the circuit can be implemented with conventional technology, but the circuit cannot operate efficiently in low voltage conditions (1V or less)
Solution Approach 1:
The patent changes the fundamental parameter of voltage threshold by using capacitive input circuits with linear or nonlinear dielectric capacitors instead of traditional transistor gates. This allows the circuit to operate at lower voltage levels (1V or less) while maintaining reliable operation, as the capacitive switching mechanism has different voltage requirements compared to traditional transistor threshold voltages.
2Area of stationary object
If asynchronous logic circuits use traditional transistor stacks, then the implementation is straightforward with conventional components, but the area occupied by the circuit is large
Solution Approach 1:
The patent extracts the input signal reception function from traditional transistor gate structures and implements it separately using capacitive input circuits. This separation allows for more compact layout and reduces the overall area occupied by the full-adder circuit while maintaining the necessary logic functionality.
Solution Approach 2:
The patent transitions from planar transistor stacking to a structure that utilizes vertical capacitor stacking in the capacitive input circuits. This dimensional change allows signals to be processed in a different spatial arrangement, reducing the horizontal area occupied by the circuit while maintaining functionality.
3Productivity
If asynchronous logic circuits use traditional transistor stacks, then the circuit structure is simple to implement, but the throughput of the circuit is limited
Solution Approach 1:
The patent introduces dynamic element matching (DEM) capacitive input circuits that can dynamically adjust their operation based on signal conditions. This dynamic behavior enables higher throughput by allowing the circuit to process signals more efficiently and reduce switching delays, while the dynamic nature adds complexity to the circuit structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables asynchronous circuits to operate at lower power supply levels with reduced area and higher throughput, achieving 3× area reduction and 2× throughput compared to traditional asynchronous circuits.
Implementation Method 1
capacitive input circuits, incorporating linear or nonlinear dielectric capacitors
Implementation Method 2
incorporating linear or nonlinear dielectric capacitors
Data Source
AI summary
Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and/or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.