Asynchronous Phase Acquisition with Dithering for Low-Noise DPLLs

Solution Overview

Problem

Digital phase locked loops face limitations in performance due to time domain quantization, particularly in terms of accuracy and noise, especially when handling multiple input signals, which requires multiple high-quality sampling clocks, increasing power consumption and complexity.

Innovation Solution

The implementation of an asynchronous digital phase locked loop with a phase acquisition unit, digital phase detector, and digital controlled oscillator, utilizing asynchronous clock detection methods and dithering techniques to improve quantization noise and accuracy, allowing for shared clock usage across multiple inputs and reducing power requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If synchronous sampling is used for multiple input signals, then sampling accuracy is improved, but power consumption and clock complexity increase due to requiring multiple high-quality sampling clocks

Engineering Contradiction:

Improvesampling accuracyVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

A single sampling clock is designed to serve multiple quantizers for different input signals, replacing the traditional requirement for separate sampling clocks for each channel. This universal clock approach reduces power consumption and clock tree complexity while maintaining acceptable sampling accuracy through careful timing design and dithering techniques

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Dithering signals with periodic characteristics are applied to the sampling process to randomize quantization errors. This periodic action helps distribute quantization noise across the frequency spectrum, improving effective sampling accuracy without requiring additional high-precision sampling clocks for each input signal

Inventive Principle:

Principle #19Periodic action

2Measurement precision

If synchronous sampling is used for multiple input signals, then sampling accuracy is improved, but device complexity increases due to requiring multiple high-quality sampling clocks

Engineering Contradiction:

Improvesampling accuracyVSAvoidclock complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

A single sampling clock is designed to serve multiple quantizers for different input signals, replacing the traditional requirement for separate sampling clocks for each channel. This universal clock approach reduces power consumption and clock tree complexity while maintaining acceptable sampling accuracy through careful timing design and dithering techniques

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Multiple sampling clock functions are merged into a single clock source. The design combines the timing requirements for multiple input signal quantization into one unified sampling clock system, reducing the number of clock generators, distribution networks, and associated control logic

Inventive Principle:

Principle #5Merging (Combining)

3Ease of manufacture

If time domain quantization is applied in digital phase locked loops, then digital processing simplicity is achieved, but accuracy and noise performance deteriorate

Engineering Contradiction:

Improvedigital processing simplicityVSAvoidaccuracy

Core Design Contradiction:

Ease of manufactureVSMeasurement precision

Solution Approach 1:

The quantization noise inherent in time domain quantization is converted from a harmful effect into a beneficial one through dithering. By intentionally adding random dither signals before quantization, the deterministic quantization errors are transformed into random noise that can be filtered more effectively, improving phase measurement accuracy while maintaining digital processing simplicity

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

Dithering signals with periodic characteristics are applied to the sampling process to randomize quantization errors. This periodic action helps distribute quantization noise across the frequency spectrum, improving effective sampling accuracy without requiring additional high-precision sampling clocks for each input signal

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS7619483B2Asynchronous phase acquisition unit with dithering

Publication Date: 2009.11.17 ZARLINK SEMICONDUCTOR INC

AI summary

A digital phase locked loop includes a phase acquisition unit receiving a sampled input signal and applying its output to a first input of a digital phase detector, a digital controlled oscillator producing a digital output, and a feedback path coupling the digital output of the digital controlled oscillator to a second input of the digital phase detector in the digital domain. The input signal may be sampled asynchronously.