Asynchronous Pipeline Timing Randomization Against Side-Channel Attacks
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Solution Overview
Problem
Cryptographic systems, particularly portable devices like smart cards, are vulnerable to side-channel attacks that exploit unsecured channels such as power usage and electromagnetic radiation, allowing attackers to extract secret information despite tamper-proof hardware, as these attacks are relatively easy and inexpensive to mount, compromising the security of the systems.
Innovation Solution
An asynchronous pipeline circuit with a programmable delay line that randomly delays request signals between processing stages, obfuscating the electromagnetic emission spectrum, making it difficult for unauthorized parties to extract secure information via side-channel attacks by transforming the signal into white noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cryptographic operations are performed in a pipeline architecture to improve processing speed, then productivity increases, but side-channel attacks can exploit timing information to extract secret data
Solution Approach 1:
The patent introduces dynamic random delays between pipeline stages that vary with each operation. This dynamic timing variation prevents attackers from correlating electromagnetic emissions with specific cryptographic operations, thereby protecting secret data while maintaining pipeline throughput.
Solution Approach 2:
The patent changes the timing parameter of signal transmission between pipeline stages by introducing random delays. This parameter modification disrupts the timing patterns that side-channel attacks rely upon, while the pipeline architecture continues to process data at high speed.
2Reliability
If random delays are introduced in the pipeline to prevent side-channel attacks, then security improves, but signal timing becomes unpredictable which may affect synchronization
Solution Approach 1:
The patent uses ready signals and acknowledgment signals as intermediaries between pipeline stages. These intermediary signals coordinate data transfer while the random delays are applied to the actual cryptographic processing signals, maintaining synchronization without compromising security.
Solution Approach 2:
The patent separates the synchronization function from the cryptographic processing function. Synchronization signals follow fixed timing patterns for reliability, while cryptographic processing signals receive random delays for security, allowing both requirements to coexist in the same pipeline architecture.
Data Source
AI summary
An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.