Logic Circuits Characterised By Logic Function TRIZ Cases

Bypassing the scan multiplexer through the master keeper path cuts critical delay while preserving Mux-D scan testability and small area.

A trigger- and comparator-based DLL control circuit pauses locking through power dips to keep DRAM read clocks synchronized and reliable.

An embedded scan chain toggles tied-off WEN paths in memory circuits to expose latent defects and improve transition coverage.

Using divide-by-N phase clocks and AND-gate selection, this case stabilizes ADC duty cycles while reducing circuit complexity and variation.

Control circuitry manages loop thread order and data dependencies in a self-reconfiguring fabric to improve compute performance and energy efficiency.

Overlapping deglitch and non-overlap delays suppress short pulses while cutting output driver propagation delay.

Serial counter stages let the first stage derive a lower-frequency clock, preventing delayed termination signals in high-speed counting.

Delta sigma control of PLL phase outputs avoids pulse swallowing and PVT sensitivity in RFPWM, extending dynamic range for WLAN signals.

By routing same-sign operands to specialized adders, this circuit cuts silicon area, power use, and latency in multi-number floating-point addition.

Proactive hop-code adjustment and offset skip correction help a DLL clock stretcher avoid wraparound glitches under supply voltage changes.

External-voltage-based duty-skew compensation helps receiver buffer circuits maintain stable output characteristics across mixed power domains.

A dual-path RC filter switches between glitch suppression and fast bypass mode, supporting I2C and I3C digital signal standards.

Dynamic clocked and holding stacks cut latch switching power and area while preserving true/complement outputs and data integrity.

Pre-reset PLL and divider bypass lowers clock frequency before partial reset, reducing current spikes and power faults in clock domains.

Pulse-driven crossbar arrays perform NAND, OR, and COPY in place, cutting data-transfer energy and simplifying Boolean and addition operations.

Sequential selector timing prevents simultaneous 5V and −4.5V application, protecting memory MOSFETs during polarity transitions.

Combining OR logic and level shifting in one MOSFET-resistor circuit cuts PCB footprint and cost while supporting mixed-voltage and legacy I/O.

A leakage-based ring oscillator converts MOS leakage into frequency for accurate on-chip temperature sensing with lower area, power, and noise sensitivity.

A negative-resistor bandpass clock filter suppresses jitter and spurious tones while preserving high Q and lowering buffer power.

Random delays between pipeline stages turn EM leakage into white noise, blocking side-channel analysis without sacrificing throughput.

Phase-divided clocks and retiming circuits adjust pulse delay and width to preserve timing margins for reliable high-speed domain crossing.

Separate calibration and delay units tune a clock to 50% duty cycle before frequency doubling, cutting phase noise, power, and circuit complexity.

Complementary driver control and balanced pull-up/pull-down paths reduce rise-fall mismatch, improving clock duty cycle accuracy.

Edge-mounted repeaters speed row and column access in dense memory subarrays without extra dummy blocks or bank splitting.

A PFD checks multiple data edges against 90° divider outputs to prevent false lock, repeated resets, and wrong clock recovery.

Separating comparison and voltage switching improves DC leakage detection accuracy while expanding excitation-unit part selection and lowering cost.

Periodic local clock suspension cuts LED driver power use while preserving PWM duty sampling and accurate brightness control.

A simplified low-speed PMOS path cuts output pad capacitance, preserving high-speed differential signaling in a dual-mode hybrid driver.

Two offset comparator paths and a hold circuit remove feedback delay in a differential hysteresis receiver, improving bandwidth and noise immunity.

Internal phase detection and feedback compensate clock-to-leveling clock skew while reducing phase adjustment circuitry and layout area.

A multi-height semi-dynamic flip-flop uses clock gate lines and optimized node placement to cut wiring capacitance, power use, and delay.

Input circuitry erases stored content during readout, enabling one-time non-volatile memory access for secure storage and irreversible counters.

Classifying operands by sign lets fixed-function same-sign adders cut power and silicon area before final mixed-sign summation.

Capacitive coupling and matched logic levels let this clock output circuit support PECL, LVDS, and HCSL voltage specs with stable low-frequency output.

Independent FPGA carry-chains are consolidated into a packed layout to cut logic cell area, routing use, latency, and power.

AOI and OAI complex gates cut clock-path transistors in a flip-flop, reducing power, area, and leakage without buffer-heavy clock inversion.

A cascaded digitally controlled oscillator and frequency-locked loop generate high-ratio clocks with lower jitter, power use, and chip area.

A common-state divisor update keeps multi-modulus dividers accurate at boundary transitions and prevents PLL lock loss.

Switching between gamma gray level sections cuts gamma line count, decoder size, and parasitic capacitance in high-resolution displays.

Spin torque sets magnetization states for reconfigurable logic, cutting standby power and heat beyond CMOS scaling limits.

Independent fault-detection circuits identify short and open transistor faults and trigger the right motor safe state even if the microcontroller fails.

A switched capacitance circuit corrects ISI-distorted clock transitions to improve duty cycle consistency while avoiding continuous power draw.

A state reinforcement circuit keeps level shifter outputs stable when a supply drops below ground, preventing unintended logic flips.

Splitting n-bit inputs into non-consecutive bit groups lets FPGA adders cut logic levels to two and reduce chip area by about 33%.

Temperature-sensed timeout control delays logic block power-down to balance leakage current against domain toggle energy across thermal conditions.

Digital logic deglitches comparator PWM spikes in a class-D amplifier using the switching clock, improving THD and PSRR without extra filters.

Multiple equivalent logic circuits, cyclic routing, and state sampling obscure power and EM patterns while preserving secure IC throughput.

A two-stage round robin arbiter pipelines user and request selection to cut latency while maintaining fair access and higher clock frequency.

Input inversion during DLL initialization replaces a longer delay line, reducing power use and clock jitter while preserving phase adjustment.

Near-threshold RNA hairpins and trigger recognition sequences enable strong, orthogonal gene repression with high fold-change control of protein expression.