Output circuit, circuit device, oscillator, electronic apparatus, and vehicle
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Solution Overview
Problem
Existing output circuits face challenges in accommodating various voltage specifications due to limitations in level-shifting mechanisms, particularly when generating clock signals according to standards like PECL, as they rely on fixed power supply voltages, making it difficult to adapt to different voltage requirements.
Innovation Solution
The proposed output circuit incorporates a first logic circuit, a capacitor, and a buffer circuit, where the logic circuit output is set to the same logic level as the buffer circuit input via the capacitor, allowing for DC component cutting and independent voltage setting, and includes latch circuits to stabilize signal levels, enabling the generation of appropriate clock signals across different voltage specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a level-shifting mechanism is used to generate clock signals according to PECL standard with fixed power supply voltage, then the clock signal output level is stable, but the circuit cannot adapt to different voltage specifications
Solution Approach 1:
The patent applies dynamics by making the power supply voltage configurable rather than fixed. The output circuit can be set to operate with different power supply voltages (e.g., 3.3V or 5V) through a voltage selection mechanism, allowing the circuit to adapt dynamically to different voltage specifications while maintaining stable clock signal output through controlled impedance matching and level shifting.
Solution Approach 2:
The patent changes the voltage parameter from a fixed value to a selectable range. By implementing voltage dividers, configurable power supply connections, and adjustable level shifting circuits, the output circuit can modify its operating voltage parameters to match different external device requirements, thereby achieving both stability and adaptability.
2Adaptability or versatility
If the logic circuit output signal level is different from the buffer circuit input node level, then level shifting can be achieved, but DC component cutting becomes problematic and signal integrity deteriorates
Solution Approach 1:
The patent introduces an intermediary buffer circuit between the logic circuit and the output stage. This buffer circuit acts as a mediator that performs controlled level shifting while maintaining DC component integrity. The buffer circuit includes voltage dividers and level shifting networks that translate signals between different voltage domains without introducing DC offsets or signal degradation.
Solution Approach 2:
The patent applies equipotentiality by ensuring that the logic circuit output and buffer circuit input operate at compatible voltage levels through configurable voltage dividers and level matching networks. This allows different voltage domains to be connected without creating potential conflicts that would degrade signal integrity.
Data Source
AI summary
Provided is an output circuit including a logic circuit, a capacitor, a buffer circuit, and a driver circuit. When a clock signal is input and an enable signal is active, the logic circuit outputs a clock signal based on the clock signal. The buffer circuit receives a signal that is an output signal of the logic circuit via the capacitor. The driver circuit outputs a clock signal based on a signal that is an output signal of the buffer circuit. The logic circuit sets a signal to the same logic level as an input node of the buffer circuit when the enable signal is inactive.