Delay-Locked Loop Control Circuit for Voltage Drop Synchronization
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Solution Overview
Problem
Conventional dynamic random access memory (DRAM) systems experience data reading errors due to asynchronous clock signals when the operation voltage drops, leading to unreliable data retrieval.
Innovation Solution
A control circuit for a delay lock loop comprising a power status detector, voltage comparator, and control signal generator that detects voltage variations, compares them with a reference voltage, and generates control signals to manage the locking operation of the delay lock loop, ensuring synchronization during power instability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock enable signal is pulled up from low logic level to high logic level to exit power down mode, then the memory can operate normally, but the operation voltage drops causing clock signal asynchrony and data reading errors
Solution Approach 1:
The control circuit detects the transition edge of the clock enable signal in advance and generates a trigger signal before the voltage drop occurs. This preliminary detection allows the system to prepare for the upcoming voltage variation and adjust the locking operation accordingly, preventing data reading errors caused by clock asynchrony
Solution Approach 2:
The control circuit continuously monitors the clock enable signal and generates control signals based on the detected transition edges and voltage comparison results. This feedback mechanism dynamically adjusts the locking operation of the delay lock loop to maintain synchronization between the clock signal and data transitions, ensuring reliable data reading
2Productivity
If the locking operation continues during voltage drop, then the delay lock loop maintains continuous operation, but data reading errors occur due to clock asynchrony
Solution Approach 1:
The control circuit operates the delay lock loop in a periodic manner by enabling the locking operation only during stable voltage periods and disabling it during voltage transitions. The control signal generator generates enable signals periodically based on detected transition edges, allowing the system to maintain continuous overall operation while avoiding errors during critical voltage drop periods
Solution Approach 2:
The control circuit generates control signals to stop the locking operation in advance when a voltage drop is detected through transition edge detection. This preliminary anti-action prevents the clock signal from becoming asynchronous with data transitions, thereby avoiding data reading errors before they can occur
Data Source
AI summary
A control circuit of delay lock loop and a control method thereof are provided. The control circuit includes a power status detector, a voltage comparator, an enable signal generator and a control signal generator. The power status detector detects a transition edge of a clock enable signal to generate a trigger signal corresponding to a variation of an operation power. The voltage comparator compares the operation power with a reference voltage to generate a comparison result. The enable signal generator sets an enable signal to an active state according to the trigger signal and sets the enable signal to a non-active state according to the comparison result. The control signal generator outputs a control clock to generate a control signal when the enable signal is in the active state.