Clock Stretcher Phase Wraparound Correction for DLL Glitches
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Solution Overview
Problem
Conventional clock stretchers require a clean power supply and struggle with glitches due to phase detector offset and finite DLL bandwidth, especially in systems with variable load conditions, leading to timing violations and functional failures.
Innovation Solution
A clock stretcher system that includes a sense unit, a delay-locked loop (DLL), and a combiner, which senses supply voltage changes and adjusts the clock frequency by selecting delayed phases cyclically, using a hop code and offset skip parameter to correct for phase detector offset and finite DLL bandwidth, allowing operation without intervening voltage regulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional clock stretcher uses a DLL with a delay line to counter supply voltage changes, then the clock frequency stability is improved, but the system cannot keep up with fast supply voltage changes due to limited DLL bandwidth, causing timing violations
Solution Approach 1:
The patent applies preliminary action by proactively detecting supply voltage changes using a sense unit before they cause timing violations, and pre-adjusting the clock frequency accordingly. The system predicts upcoming voltage droops and stretches the clock cycle in advance, rather than reacting after the violation occurs. This is evident in the description where the sense unit detects voltage changes and the control unit adjusts the hop code to modify clock frequency proactively.
Solution Approach 2:
The patent introduces an intermediary sense unit that monitors supply voltage changes and communicates this information to the control unit, which then adjusts the DLL operation. This intermediary detection mechanism allows the system to respond to voltage changes without relying solely on the limited bandwidth of the DLL feedback loop. The sense unit acts as a mediator between the power supply and the clock generation circuitry.
2Measurement precision
If the delay line is designed with high resolution to improve clock frequency control precision, then the manufacturing precision is improved, but the power consumption and die area increase
Solution Approach 1:
The patent applies dynamics by making the delay line resolution adaptive rather than fixed. The system dynamically adjusts the effective resolution of the delay line based on the magnitude of supply voltage changes detected by the sense unit. When voltage changes are small, finer resolution is used; when changes are large, coarser resolution suffices. This is achieved through the control unit's ability to vary the hop code and select different phases from the delay line, effectively adapting the precision to the actual operating conditions.
Solution Approach 2:
The patent changes the operational parameters of the delay line by varying the hop code and phase selection based on detected supply voltage conditions. Instead of using a fixed high-resolution delay line, the system dynamically adjusts which delay elements are accessed and how the phase is selected, effectively changing the resolution parameter to match the actual precision requirements of the current operating condition.
3Ease of operation
If a digital DLL is used to eliminate the need for a clean power supply, then the ease of operation is improved, but glitches occur at the time of DLL adjustment causing timing violations
Solution Approach 1:
The patent applies preliminary anti-action by detecting when DLL adjustments are about to occur and proactively compensating for the expected glitches. The sense unit monitors supply voltage changes that would trigger DLL reconfiguration, and the control unit pre-adjusts the clock frequency or selects appropriate phases to counteract the upcoming glitch. This anticipatory compensation prevents timing violations before they can occur during DLL adjustments.
Solution Approach 2:
The patent uses feedback from the sense unit that continuously monitors supply voltage and detects when conditions warrant DLL adjustment. This feedback mechanism allows the control unit to coordinate DLL reconfiguration with the current clock phase and voltage conditions, minimizing the impact of adjustment glitches. The system feedback loop ensures that DLL changes are made at optimal moments and with appropriate compensation.
4Stability of the object's composition
If the DLL feedback loop bandwidth is limited to ensure stability, then the stability is improved, but the system cannot respond to fast supply voltage changes, causing functional failures
Solution Approach 1:
The patent applies preliminary action by having the sense unit detect supply voltage changes before they become critical, allowing the control unit to prepare appropriate compensation actions. Rather than relying on the slow DLL feedback loop to react to voltage changes, the system proactively adjusts the clock frequency in advance, maintaining stability while responding quickly to voltage variations.
Solution Approach 2:
The sense unit serves as an intermediary that bridges the gap between the power supply and the stable but slow DLL feedback loop. It detects voltage changes and communicates this information to the control unit, which then adjusts the clock generation accordingly. This intermediary mechanism allows the stable DLL to maintain its low bandwidth while the system as a whole responds quickly to voltage changes.
Data Source
AI summary
A clock stretcher includes a DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. The DLL may have a phase error that would cause a glitch in the modified clock during phase selection wraparound. The clock stretcher proactively increases the step size during wraparound by adding an offset skip parameter value to the hop code. The clock stretcher may operate from a sensed power supply without intervening voltage regulation.