Clock Recovery Circuit for Correct Frequency and Phase Lock
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Solution Overview
Problem
Clock data recovery systems face issues with incorrect frequency and phase locking, leading to repeated resets and inefficiencies, especially when data rates vary widely and incorrect phase locking occurs, resulting in incorrect data recovery.
Innovation Solution
A circuit incorporating a voltage-controlled oscillator (VCO), phase-frequency detector (PFD), and frequency divider that detects specific edge conditions to adjust the frequency and phase of the feedback clock, ensuring accurate lock by asserting FASTER or SLOWER signals to increase or decrease the VCO frequency, thereby maintaining phase and frequency synchronization with the received data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the receiver uses a traditional phase-frequency detector to recover clock from Manchester-encoded data, then the clock can be recovered, but incorrect frequency and phase locking occurs leading to repeated resets and data recovery errors
Solution Approach 1:
The patent applies preliminary action by detecting multiple edges (at least two edges) of the data signal within a single period of the frequency divider signal before making frequency adjustment decisions. This preliminary detection prevents premature or incorrect frequency adjustments that would otherwise cause the repeated locking failures and resets described in the contradiction.
2Speed
If the VCO frequency is adjusted based on single edge detection, then frequency locking can be achieved, but incorrect phase locking occurs resulting in wrong data recovery
Solution Approach 1:
The patent performs preliminary detection of multiple data edges during one period of the frequency divider signal before asserting FASTER or SLOWER signals. This ensures that frequency adjustments are based on comprehensive edge information rather than premature single-edge detection, thereby achieving both fast and accurate phase locking without the errors described in the contradiction.
3Reliability
If the system continuously monitors and adjusts VCO frequency to maintain synchronization, then data recovery accuracy improves, but power consumption increases
Solution Approach 1:
The patent implements periodic action by monitoring data edges only at specific intervals synchronized with the frequency divider signal period. Rather than continuous monitoring, the system checks for multiple edges during discrete periods and adjusts VCO frequency accordingly. This periodic approach maintains accurate data recovery while significantly reducing power consumption compared to continuous monitoring and adjustment.
Data Source
AI summary
A circuit includes a voltage-controlled oscillator (VCO) and a frequency divider. The frequency divider input is coupled to the VCO output. The circuit further includes a phase-frequency detector (PFD). A control output of the PFD is coupled to the VCO. A first PFD input is coupled to a first frequency divider output, and a second PFD input is coupled to a second frequency divider output. The first frequency divider output is configured to provide a first frequency divider signal and the second frequency divider output is configured to provide a second frequency divider signal 90 degrees out of phase with respect to the first frequency divider signal. The PFD is configured to detect an occurrence of at least two edges of a signal on the data input while the second frequency divider signal is continuously logic high across the at least two edges.