Memory Array Edge Repeater Layout for Faster Dense Subarray Access
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Solution Overview
Problem
In memory devices used for AI and machine learning applications, the increasing memory density leads to array accessing speed degradation due to long parasitic capacitance and resistance, and existing solutions that improve speed, such as adding repeaters, increase the chip size by requiring additional dummy blocks.
Innovation Solution
The memory device incorporates a plurality of subarrays with edge-mounted repeaters, subword drivers, and sense amplifiers, allowing for improved column and row accessing speeds without splitting memory cells into multiple banks, thus avoiding the need for additional dummy blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory density is increased to meet AI and machine learning application requirements, then memory capacity is improved, but array accessing speed degrades due to long parasitic capacitance and resistance
Solution Approach 1:
The memory array is divided into multiple subarrays, and the word driver is segmented into multiple components (first word driver component and second word driver component) that can independently drive different subarrays. This segmentation reduces the effective drive distance for each component, lowering parasitic capacitance and resistance effects, thereby maintaining faster access speeds while supporting higher memory density.
Solution Approach 2:
A repeater is introduced as an intermediary component between the decoders and the subarrays. The repeater receives selector signals from the column decoder and row decoder, amplifies them, and redistributes them to the respective subarrays. This intermediary function reduces the loading stress on the original selector lines, effectively combating the speed degradation caused by long parasitic capacitance and resistance in high-density configurations.
2Speed
If a repeater is added in the center of memory cells to reduce loading stress, then array accessing speed is improved, but chip area increases due to additional dummy blocks
Solution Approach 1:
The repeater is designed to serve multiple functions simultaneously: it acts as a signal amplifier for both column and row selector lines, provides signal regeneration, and reduces loading stress on decoders. By consolidating these functions into a single component placed at the edge of subarrays rather than requiring separate dummy blocks, the design achieves speed improvement without proportionally increasing chip area.
Solution Approach 2:
Instead of placing the repeater in the traditional center position of memory cells (which requires dummy blocks and increases area), the repeater is repositioned to the edge of subarrays. This dimensional repositioning allows the repeater to serve multiple subarrays efficiently while utilizing existing peripheral structures, thereby improving access speed without requiring additional dummy blocks and minimizing area increase.
3Speed
If memory cells are split into multiple banks to improve accessing speed, then array accessing speed is improved, but device complexity increases due to additional column decoders, row decoders, and sense amplifiers
Solution Approach 1:
Multiple subarrays are merged under a single shared decoder structure and sense amplifier system. The first and second word driver components can independently drive different subarrays, but they share common control logic and decoding resources. This merging approach maintains the speed benefits of segmented driving while avoiding the complexity multiplication that would result from fully independent bank structures.
Solution Approach 2:
The word driver is designed with dynamic switching capability, where the first and second word driver components can be selectively activated based on which subarray needs to be accessed. This dynamic operation allows the system to maintain simplicity by using shared resources while achieving the speed benefits of segmented architecture through time-multiplexed access to different subarrays.
Data Source
AI summary
A memory device is provided. The memory device includes: a plurality of subarrays, a row control, a column control, a plurality of sense amplifiers, a plurality of sub word drivers, and a repeater. Each of the subarrays are electrically coupled to each other. The row control is configured to control at least a row of the subarrays. The column control is configured to control at least one column of the subarrays. The sense amplifiers are adapted to each of the subarrays are periodically enabled during a data access operation. The sub word drivers are disposed adjacent to each of the subarrays and provides a driving signal corresponds to the subarrays. The repeater is configured to disposed on the edge of the subarrays.