Multi-Modulus Divider State Control for Stable PLL Lock
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multi-modulus dividers (MMDs) fail to accurately reduce signal frequencies across unstable division range boundaries, leading to PLL lock loss and instability, especially when divisor values transition across boundaries like 63-64 or 127-128.
Innovation Solution
The implementation of a multi-modulus divider with a control circuit that applies a divisor value only during a state common to all possible divisor values, preventing the divider from entering unknown states and ensuring accurate frequency division across these boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional multi-modulus dividers are used to reduce signal frequency, then frequency division is achieved, but accuracy is lost at unstable division range boundaries (e.g., 63-64 or 127-128)
Solution Approach 1:
The patent applies preliminary action by pre-defining a specific state (e.g., all counter bits at logic 0 or logic 1) as the common reference state before divisor value transitions. The control circuit is designed to detect when the counter reaches this predetermined state and uses it as a trigger point to safely update the divisor value, ensuring the transition occurs at a known, stable configuration rather than at arbitrary boundary points.
Solution Approach 2:
The patent implements feedback by using the counter's current state as input to the control circuit, which monitors whether the counter has reached the common state. Based on this feedback, the control circuit determines the appropriate timing for updating the divisor value. This closed-loop feedback mechanism ensures that divisor transitions only occur when the counter is in the predetermined common state, maintaining accuracy across all division range boundaries.
2Adaptability or versatility
If divisor values are updated continuously in conventional MMDs, then frequency tuning flexibility is improved, but the divider enters unknown states causing PLL lock loss
Solution Approach 1:
The patent prepares the system for safe divisor transitions by establishing a predetermined common state as a mandatory checkpoint. Before allowing any divisor value update, the system waits for the counter to reach this pre-defined state, ensuring that transitions occur only from a known, stable configuration. This preliminary preparation prevents the divider from entering unknown states during frequency tuning operations.
Solution Approach 2:
The control circuit continuously monitors the counter state and uses this feedback to control when divisor updates occur. The feedback mechanism ensures that divisor values are only updated when the counter reaches the common state, creating a controlled update rhythm that maintains PLL lock while still allowing flexible frequency tuning across the full range of divisor values.
3Adaptability or versatility
If the MMD operates across wide division ranges, then frequency synthesis flexibility is improved, but noise and interference increase
Solution Approach 1:
By pre-defining a common state as the mandatory transition point, the patent ensures that all divisor value changes occur under controlled, identical conditions. This preliminary setup creates consistency in the division operation across the entire frequency range, reducing variability-induced noise and interference that would otherwise increase with wide division ranges.
Solution Approach 2:
The feedback-controlled update mechanism ensures that divisor transitions occur only when the counter is in the common state, creating a regular and predictable operation pattern. This feedback enforcement reduces jitter and timing variations that contribute to noise, allowing the system to operate across wide division ranges with minimized harmful interference.
Data Source
AI summary
Various embodiments relate to multi-modulus frequency dividers, devices including the same, and associated methods of operation. A method of operating a multi-modulus divider (MMD) may include receiving, at the MMD, an input signal at a first frequency. The method may also include generating, via the MMD, an output signal at a second, lower frequency based on a divisor value. Further, the method may include receiving, at the MMD, an integer value. Moreover, the method may include setting the divisor value equal to the integer value in response to a current state of the MMD matching a common state for the MMD, wherein the MMD is configured to enter the common state regardless of the divisor value.