Receiver Buffer Circuit With Duty-Skew Compensation Across Voltage Domains

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Solution Overview

Problem

Semiconductor receiver circuits face challenges in maintaining stable output characteristics due to variations in heterogeneous power supply voltages, which affect data reception and processing.

Innovation Solution

The implementation of a buffer circuit configuration that includes first and second logic gates coupled to internal and external voltage terminals, enabling data inversion and compensation for duty skew based on enable signals and reference voltages, ensuring stable output regardless of power supply voltage fluctuations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a receiver circuit operates with heterogeneous power supply voltages (external and internal), then the circuit can be designed with flexibility in voltage sources, but the output characteristics become unstable due to voltage variations

Engineering Contradiction:
Improvevoltage source flexibilityVSAvoidoutput characteristic stability
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the compensation amount based on the external voltage level. When the external voltage changes, the compensation circuit modifies its compensation amount to counteract the duty skew, thereby maintaining stable output characteristics despite voltage variations. This is achieved by changing the operational parameters of the compensation circuit in response to voltage fluctuations.

Inventive Principle:
Principle #35Parameter changes

2Stability of the object's composition

If a buffer circuit is designed to compensate for duty skew, then output stability is improved, but the circuit complexity increases due to additional logic gates and control mechanisms

Engineering Contradiction:
Improveoutput signal stabilityVSAvoidbuffer circuit structure
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The buffer circuit is segmented into distinct functional modules: a first logic gate for data inversion, a second logic gate for output inversion, and a compensation circuit for duty skew correction. This segmentation allows each module to perform a specific function, making the overall complex circuit more manageable and easier to design while achieving stable output characteristics through coordinated operation of the segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The compensation circuit acts as an intermediary between the logic gates and the output, mediating the duty skew caused by voltage variations. By introducing this intermediate compensation stage, the circuit maintains stable output characteristics without requiring complete redesign of the entire buffer structure, thus balancing complexity and performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the buffer circuit compensates for duty skew based on external voltage level, then output stability under voltage variation is improved, but the control mechanism becomes more complex

Engineering Contradiction:
Improveoperational reliability under voltage variationVSAvoidcontrol mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The compensation circuit employs a feedback mechanism where the external voltage level is monitored and used to determine the appropriate compensation amount. This feedback loop allows the circuit to automatically adjust its compensation in response to voltage variations, improving reliability under varying conditions while keeping the control mechanism relatively simple through automatic adjustment rather than complex external control.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11233512B2Buffer circuit, receiver circuit including the buffer circuit, and semiconductor apparatus including the receiver circuit
Publication Date: 2022.01.25 SK HYNIX INC
  • US11233512B2 patent drawing
  • US11233512B2 patent drawing
  • US11233512B2 patent drawing

AI summary

The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.