Negative-Resistor Clock Filter for Jitter and Spurious Noise
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Solution Overview
Problem
Integrated circuits face challenges with internal clock signal degradation due to co-existing digital signals, which introduce jitter and spurious tones, and routing buffers contribute to noise and increased power consumption.
Innovation Solution
A clock filter circuit incorporating a negative resistor circuit and bandpass filters with trimmable capacitors is used to attenuate noise and improve the quality factor, comprising inverters, capacitors, and inductors, with a sampling circuit to tune the center frequency and prevent voltage sticking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If routing buffers are added to the clock signal path, then the clock signal can be distributed to multiple functional circuits, but noise is introduced and power consumption increases
Solution Approach 1:
The patent extracts the clock signal distribution function from traditional routing buffers by using a shared clock filter circuit that can serve multiple functional circuits simultaneously, thereby eliminating the need for separate buffers at each destination and reducing overall noise generation
Solution Approach 2:
The patent merges multiple clock signal distribution paths into a single shared clock filter circuit that serves multiple functional circuits, reducing the total number of active components and minimizing cumulative noise while maintaining distribution capability
2Adaptability or versatility
If routing buffers are added to the clock signal path, then the clock signal can be distributed to multiple functional circuits, but power consumption increases
Solution Approach 1:
The patent merges multiple clock signal distribution paths into a single shared clock filter circuit, reducing the total number of active buffering components and thereby lowering cumulative power consumption while maintaining the ability to distribute clock signals to multiple functional circuits
3Productivity
If digital signals co-exist on the chip, then functional circuits can be integrated, but the clock signal degrades with jitter and spurious tones
Solution Approach 1:
The patent introduces a dedicated clock filter circuit as an intermediary component between the clock signal source and multiple functional circuits, specifically designed to filter out jitter and spurious tones caused by digital signal interference while allowing the integrated circuits to coexist on the same chip
Solution Approach 2:
The patent applies local quality enhancement by placing a specialized clock filter circuit at the clock signal distribution point, providing targeted noise filtering specifically for the clock signal path without affecting other digital signal operations on the chip
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively attenuates noise and spurious signals while maintaining a high quality factor, reducing power consumption and immunity to power supply and ground noise, allowing for smaller inverter sizes and precise frequency tuning.
Implementation Method 1
The negative resistance circuitry is coupled to a output of the filter. The negative resistance circuitry compensates for energy loss in the filter.
Implementation Method 2
In one example, the filter is a bandpass filter that passes through a clock signal at a center frequency equal to a frequency of the clock signal
Implementation Method 3
the filter includes four capacitors, three inductors, and a resistor
Data Source
AI summary
A circuit includes a filter, a first inverter, and a second inverter. The filter is coupled to an input of the first inverter. The second inverter includes an input and an output. The input of the second inverter is coupled to the output of the first inverter. The output of the second inverter is coupled to the input of the first inverter.