Mux-D Scan Flip-Flop Topology That Bypasses Multiplexer Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flip-flop designs in microprocessors face challenges with scan logic overhead, which consumes significant area and delays frequency, while traditional Mux-D scan flip-flops have performance limitations and cannot be converted into bare pass-gate versions.
Innovation Solution
A novel fast Mux-D scan flip-flop design that bypasses the traditional input data scan multiplexer to the master keeper side path, reducing delay overhead and allowing compatibility with simple scan methodologies, preserving high performance similar to level sensitive scan designs and enabling conversion to bare pass-gate versions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional Mux-D scan flip-flop design is used, then scan logic is included for testing, but scan logic consumes approximately 70% of standard cell size and limits frequency due to critical delay
Solution Approach 1:
The patent segments the scan path into two separate paths: a fast scan path that bypasses the multiplexer for critical timing paths, and a traditional scan path for non-critical paths. This segmentation allows the fast path to avoid the 70% area overhead and delay penalties of traditional Mux-D scan while maintaining testability through the separate fast scan infrastructure.
Solution Approach 2:
The patent introduces an intermediary fast scan path that acts as a mediator between the test requirements and the performance-critical data path. This intermediary path provides scan capability without requiring the traditional multiplexer structure, thereby resolving the contradiction between testability and performance/area overhead.
2Reliability
If traditional Mux-D scan flip-flop design is used, then scan logic is included, but area overhead is significant and performance is limited
Solution Approach 1:
The patent segments the scan functionality into a fast scan path that uses minimal area overhead compared to traditional Mux-D scan. The fast scan path is specifically designed for area-constrained applications while maintaining testability, reducing the area overhead from 70% to a significantly smaller footprint.
3Reliability
If traditional Mux-D scan flip-flop design is used, then scan logic is included, but delay overhead limits frequency performance
Solution Approach 1:
The patent segments the scan path to create a fast scan path that bypasses the multiplexer delay entirely. This fast path is dedicated to timing-critical paths and uses a simplified structure that eliminates the delay overhead inherent in traditional Mux-D scan, thereby improving frequency performance while maintaining testability.
Solution Approach 2:
The patent implements a fast scan path that allows test signals to skip through the multiplexer structure entirely and reach the flip-flop input directly. This skipping mechanism eliminates the delay overhead of the multiplexer, enabling higher frequency operation while preserving scan testability.
4Speed
If level sensitive scan design is used, then performance is high, but area overhead and complexity are larger compared to Mux-D scan
Solution Approach 1:
The patent creates a simplified copy of the level-sensitive scan approach specifically for the fast scan path. Instead of implementing the full level-sensitive scan structure, it copies only the essential bypass mechanism that provides high performance, while using a different structure for the traditional scan path, thereby achieving LSSD-like performance with reduced complexity.
Data Source
AI summary
A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.