Embedded Memory Scan Chain for Tied-Off Logic Cone Testing
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Solution Overview
Problem
Tied-off logic cones in memory circuits, resulting from disabled logic features, lack observability and full testability, leading to undetectable latent faults, particularly when the bit-write mask function is disabled, which affects transition coverage and fault detection in safety-critical applications.
Innovation Solution
The implementation of an embedded scan chain with input and output phase circuits that include multiplexers and latches, allowing the write-enable bit to be selectively toggled between high and low logic values during a scan operation, even when the bit-write mask function is disabled, thereby enhancing controllability and observability of tied-off logic cones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the bit-write mask function is disabled and WEN inputs are tied-off to low logic state, then device complexity is reduced and manufacturing is simplified, but testability and fault detection capability deteriorate
Solution Approach 1:
The patent segments the scan chain into separate controllable paths for WEN inputs and D inputs. By dividing the testing mechanism into independent segments, the WEN scan chain can be controlled separately even when the bit-write mask function is disabled, allowing fault detection in previously unttestable logic cones while maintaining the simplified manufacturing approach.
Solution Approach 2:
The patent introduces an intermediary scan chain structure that mediates between the disabled bit-write mask function and the testing requirement. The separate WEN scan chain acts as an intermediary mechanism that provides test control to WEN inputs without requiring the bit-write mask function to be enabled, thus resolving the contradiction between simplified manufacturing and fault detection capability.
2Ease of operation
If logic features are de-selected or disabled for specific applications, then device complexity is reduced and ease of operation is improved, but observability and testability of logic cones deteriorate
Solution Approach 1:
The patent implements dynamic controllability by making the scan chain configuration adaptable to different operating modes. The scan enable signal and separate WEN scan chain allow the system to dynamically switch between functional mode (where WEN inputs are tied-off) and test mode (where WEN inputs are controllable), ensuring both ease of operation for specific applications and comprehensive test coverage.
Solution Approach 2:
The patent creates a universal scan chain architecture that serves multiple functions: it supports both applications where bit-write mask is enabled and applications where it is disabled. The separate WEN scan chain provides multi-functionality by enabling testing in both configured and unconfigured states, thus maintaining reliability and test coverage across different application scenarios.
3Device complexity
If WEN inputs are tied-off to low logic state, then device complexity is reduced, but transition coverage during scanning deteriorates
Solution Approach 1:
The patent segments the scanning function into separate WEN scan chain and D scan chain. This segmentation allows independent control of WEN inputs during scanning, enabling transition coverage testing for WEN-related logic cones even when WEN inputs are tied-off in normal operation. The simplified device complexity is maintained while achieving comprehensive transition coverage through the separate scan path.
Data Source
AI summary
A memory circuit includes input multiplexers passing one of a pair of input bits. A first input multiplexer receives a first data bit and a serial input bit. Additional input multiplexers receive either a respective pair of data (D) bits, or a write-enable (WEN) bit and a single D bit. Scan latches receive one of the input bits and provide a scan output bit. OR gates arranged receive the scan output bit from a different scan latch, and perform a logical OR operation thereon to generate an OR output bit. Downstream output multiplexers pass a corresponding bit from a bit array or the OR output bit from a corresponding OR gate, and sense latches receive the corresponding bit from one of the output multiplexers and provide a sense output bit. Each sense output bit feeds into one or more input multiplexers when a bit-write-mask function is disabled.