Integrated Deglitcher Circuit for Non-Overlap Driver Timing
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Solution Overview
Problem
Conventional output drivers experience significant signal propagation delay due to deglitcher and nonoverlap blocks, which suppress glitches but also increase driver delay, making it challenging to reduce delay without affecting performance.
Innovation Solution
Integrating nonoverlap delay into the deglitcher delay by using two deglitcher circuits with different delays, where one circuit's output serves as the mode control for the other, allowing for efficient suppression of glitches and ensuring transistors do not overlap, thereby reducing total driver delay without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deglitcher delay is increased to suppress glitches, then glitch suppression performance is improved, but driver delay increases
Solution Approach 1:
The patent combines the deglitcher delay and nonoverlap delay into a single integrated delay circuit. The first deglitcher circuit and second deglitcher circuit share a common mode control signal and are merged into one unified structure, allowing both glitch suppression and nonoverlap timing to be achieved simultaneously without the need for separate delay blocks, thereby reducing total driver delay while maintaining glitch suppression performance.
Solution Approach 2:
The integrated deglitcher circuit performs multiple functions: it provides deglitching for both outp and outn signals, generates nonoverlap timing, and produces mode control signals for itself. By making the delay circuit universal and multi-functional, the patent eliminates redundant delay blocks while maintaining all necessary timing functions, thus resolving the contradiction between glitch suppression and driver delay.
2Reliability
If nonoverlap delay is increased to ensure transistors do not overlap, then transistor non-overlap reliability is improved, but driver delay increases
Solution Approach 1:
The patent merges the nonoverlap delay function into the deglitcher delay circuitry. The first and second deglitcher circuits are designed such that their delay paths are integrated and share common control signals, allowing nonoverlap timing to be achieved within the existing deglitcher delay structure rather than adding separate nonoverlap delay blocks, thus maintaining reliability while reducing total delay.
Solution Approach 2:
The integrated deglitcher circuit performs preliminary timing actions by using the mode control signal to pre-coordinate the switching of outp and outn signals. The circuit proactively manages the timing relationships between transistors through the shared mode control signal, ensuring non-overlap conditions are met before potential conflicts arise, thereby maintaining reliability without requiring additional delay time.
Data Source
AI summary
A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.