Logic Circuit Adder Layout for Low-Latency FPGA Summation
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Solution Overview
Problem
Existing FPGA configurations for adding multiple-bit binary numbers, such as 3:1 adders, experience higher latency and consume more chip area due to the inefficiency of current adder tree structures, particularly in digital signal processing and mathematical operations.
Innovation Solution
The implementation of a logic circuit with 2.5:1 adders that split multiple-bit inputs into non-consecutive binary strings and route them through separate adders, reducing the number of logic levels and chip area required, while maintaining efficient addition operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 3:1 adders are used to sum multiple-bit binary numbers, then the number of addition operations is reduced, but latency increases and chip area consumption increases due to exceeding look-up table capacity limits
Solution Approach 1:
The patent segments the multiple-bit binary inputs into non-consecutive binary strings (e.g., even-position bits and odd-position bits separated into different groups). This segmentation allows each adder to process only a subset of bit positions, reducing the capacity requirements of individual adders and look-up tables to fit within XILINX FPGA limits, while still achieving efficient parallel summation of all inputs
Solution Approach 2:
The patent introduces a new dimension to the addition problem by processing non-consecutive bit positions in parallel across multiple adders. Instead of sequentially adding all bits through a single adder tree, the invention distributes bit processing across multiple dimensions (different adder units handling different bit position groups), reducing latency to two logic levels while maintaining accurate summation
2Productivity
If 3:1 adders are configured on XILINX FPGAs, then addition capacity is increased, but chip area increases by 33% due to look-up table capacity constraints
Solution Approach 1:
The patent segments the multiple-bit binary inputs into non-consecutive binary strings (e.g., even-position bits and odd-position bits separated into different groups). This segmentation allows each adder to process only a subset of bit positions, reducing the capacity requirements of individual adders and look-up tables to fit within XILINX FPGA limits, while still achieving efficient parallel summation of all inputs
Solution Approach 2:
The patent applies partial action by having each adder process only a portion of the total bit positions (specifically, non-consecutive groups). Each adder performs addition on a subset of inputs rather than all inputs, which reduces the resource requirements per adder to fit within chip area constraints while the collective system achieves the full addition capacity
Data Source
AI summary
A logic circuit comprising: inputs for receiving multiple n-bit numbers, n being greater than one; and an adder capable of receiving m n-bit numbers, m being greater than one, and forming an output representing the sum of those numbers, the adder having a plurality of single-bit stages and being configured to form the sum by subjecting successive bits of each of the numbers to an operation in a respective one of the single-bit stages, the single-bit stages being such that the adder has insufficient capacity to add all possible combinations of bits in a respective bit position of m n-bit numbers; the addition circuit being configured to add the multiple n-bit numbers by: in the adder, adding a first one of the n-bit numbers to a value corresponding to a set of non-consecutive bits of another of the n-bit numbers to form a first intermediate value; adding the first intermediate value to a value corresponding to the bits of the said other of the n-bit numbers other than those in the said set to form a sum; and outputting the sum.