DLL Timing Adjustment Using Input Inversion to Cut Jitter
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Solution Overview
Problem
Traditional delay locked loops (DLLs) in semiconductor devices consume significant power and contribute to clock jitter, particularly at lower data rates due to the length of the delay line required for phase adjustment.
Innovation Solution
Inverting the input signal during the DLL initialization process instead of delaying it beyond a 180-degree phase shift, which reduces the length of the variable delay line and minimizes power consumption without increasing circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a longer delay line is used in traditional DLL to support lower data rates, then phase adjustment capability is improved, but power consumption increases
Solution Approach 1:
The patent inverts the input signal during DLL initialization instead of delaying it beyond a 180-degree phase shift. This inversion approach allows the delay line to be shorter while still achieving the required phase adjustment range, thereby reducing power consumption without sacrificing adaptability.
Solution Approach 2:
The patent determines an accurate delay amount during the DLL initialization process and uses this information to optimize the delay line operation. By dynamically adjusting the delay parameters based on actual measurements rather than using a fixed long delay line, the system achieves necessary phase adjustment with reduced power consumption.
2Adaptability or versatility
If a longer delay line is used in traditional DLL, then phase adjustment capability is improved, but clock jitter increases
Solution Approach 1:
By inverting the input signal rather than using a long delay line to achieve phase adjustment, the patent reduces the delay line length which in turn reduces clock jitter while maintaining the ability to provide variable phase adjustments across the required range.
Solution Approach 2:
The patent determines an accurate delay amount during initialization and uses this optimized parameter to minimize the delay line length, thereby reducing clock jitter while still achieving the necessary phase adjustment capability through controlled parameter adjustment.
3Use of energy by moving object
If delay amount is determined during DLL initialization, then power consumption is reduced, but initialization complexity increases
Solution Approach 1:
The patent incorporates signal inversion as part of the DLL initialization sequence. This approach determines the accurate delay amount through a systematic initialization process that, while adding steps, uses straightforward signal inversion and measurement techniques rather than complex algorithms, thus reducing power consumption with manageable initialization complexity.
4Use of energy by moving object
If delay line length is reduced, then power consumption is reduced, but phase adjustment range is limited
Solution Approach 1:
The patent compensates for the reduced delay line length by inverting the input signal, which effectively extends the achievable phase adjustment range. The inversion provides an additional 180 degrees of phase shift, allowing a shorter delay line to achieve the same total phase adjustment capability as a longer traditional delay line, thereby reducing power consumption while maintaining adaptability.
Data Source
AI summary
An electronic device including: a delay circuit configured to adjust a delay of an input for generating an output signal; and an input selection circuit coupled to the delay circuit, the input selection circuit configured to control a phase for a clock input based at least in part on a measurement of a delay corresponding to the delay circuit in generating the input.