PLL And Divider Bypass Sequencing for Low-Power Clock Reset
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Solution Overview
Problem
Infotainment system-on-a-chip (SoC) experiences high power consumption during partial reset, leading to potential power faults and non-compliance with customer specifications due to increased power usage in clock domains.
Innovation Solution
The integration of clock management logic with PLL and divider bypass mechanisms, combined with delay logic, reduces current levels during partial reset by lowering clock rates and staggered bypass control signals to manage clock domains effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a partial reset is performed in a synchronous reset mechanism, then the reset function is achieved, but power consumption increases significantly (1.5× to 4× higher than functional mode)
Solution Approach 1:
The patent applies preliminary action by asserting the PLL bypass control signal before the reset signal is asserted. This preliminary bypass action reduces the clock frequency to a lower frequency before the reset occurs, thereby reducing power consumption during the reset interval. The bypass logic is activated in advance to ensure that when reset happens, the clock domains are already operating at reduced power levels.
Solution Approach 2:
The patent implements dynamics by dynamically switching the clock frequency based on the reset state. The bypass logic dynamically adjusts the clock signal path - during functional mode, full-speed clocks are provided to clock domains, but during reset mode, the system dynamically switches to a lower frequency clock path through the bypass logic, optimizing power consumption according to the operational state.
2Reliability
If full reset is performed, then complete system reset is achieved, but power consumption and reset duration increase
Solution Approach 1:
The patent applies segmentation by dividing the reset mechanism into two types: full reset for complete system reset and partial reset for selective clock domain reset. The bypass logic is integrated into the clock management system to enable partial reset operations on specific clock domains without affecting the entire system. This segmentation allows the system to choose the appropriate reset scope, reducing unnecessary reset duration and power consumption while maintaining reset completeness when needed.
3Speed
If clock domains operate at full frequency during reset, then clock functionality is maintained, but power consumption exceeds customer specifications
Solution Approach 1:
The patent applies preliminary action by asserting the PLL bypass control signal before the reset signal is asserted. This preliminary bypass action reduces the clock frequency to a lower frequency before the reset occurs, thereby reducing power consumption during the reset interval. The bypass logic is activated in advance to ensure that when reset happens, the clock domains are already operating at reduced power levels.
Solution Approach 2:
The patent implements parameter changes by changing the clock frequency parameter during reset operations. The bypass logic modifies the operational parameters of the clock domains by switching from full-frequency operation to lower-frequency operation during reset intervals. This parameter change directly reduces power consumption while maintaining sufficient clock functionality for reset operations.
Data Source
AI summary
An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.