Two-Phase Flip-Flop Clock Output With Symmetrical Rise and Fall

The patent applies asymmetry by using different numbers of serially-coupled inverters for the true and complementary clock signals. Specifically, one path uses two serially-coupled inverters while the other uses three, creating intentionally asymmetric delay paths that compensate for the inherent asymmetry in P-type and N-type circuit drive strengths, thereby equalizing rise and fall times.

The patent changes the parameter of inverter delay by varying the number of serially-coupled inverters in different clock paths. This parameter adjustment allows fine-tuning of signal propagation delays to compensate for drive strength mismatches, ensuring symmetrical rise and fall times despite using conventional P-type and N-type circuits.

The patent segments the clock distribution network into multiple independent paths, each with its own series of serially-coupled inverters. This segmentation allows independent optimization of each path's delay characteristics while maintaining overall system simplicity through modular design.

The patent adjusts the parameter of inverter count in each clock path to achieve the desired delay balance. By changing only the number of inverters rather than modifying transistor dimensions or adding complex control logic, the solution achieves duty cycle accuracy with minimal increase in circuit complexity.