Dynamic Dual-Output Latch Circuit With Low Clock Load
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Solution Overview
Problem
Existing integrated circuits face high switching power consumption due to significant clock contributions, large transistor counts, and polysilicon pitch area requirements, which hinder efficient power management and chip area optimization.
Innovation Solution
A low clock load dynamic dual output latch circuit design featuring dynamic clocked stacks and holding stacks, utilizing fewer transistors and optimized transistor configurations to reduce switching power and capacitance load, while maintaining data integrity through non-interfering evaluation and keeper mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional flop designs are used, then data storage functionality is achieved, but switching power consumption increases significantly
Solution Approach 1:
The latch circuit is divided into two independent stages: a dynamic clocked stage for data capture and a holding stage for data maintenance. This segmentation allows each stage to be optimized independently, with the holding stage using fewer transistors (3 transistors) compared to conventional designs, thereby reducing overall switching power consumption while maintaining data storage functionality.
Solution Approach 2:
The patent employs dynamic clocked stacks that operate in a time-dependent manner, where transistors are activated only when needed during clock edges. This dynamic operation reduces the number of transistors that need to be continuously driven, lowering the capacitive load and switching power consumption compared to static latch designs.
2Reliability
If more transistors are used in latch circuits, then data storage reliability improves, but chip area increases
Solution Approach 1:
By segmenting the latch into dynamic clocked stacks and holding stacks with distinct functions, the design achieves reliable data storage through functional specialization rather than increasing transistor count. The holding stage maintains data with minimal transistors, reducing chip area while preserving reliability through the two-stage architecture.
Solution Approach 2:
Different regions of the circuit are assigned different transistor densities based on functional requirements. The dynamic clocked stage uses sufficient transistors for reliable data capture during active clock phases, while the holding stage uses minimal transistors for data maintenance, optimizing the local transistor distribution to balance reliability and area.
Data Source
AI summary
The present disclosure relates to integrated circuits, and more particularly, to a low clock load dynamic dual output latch circuit and methods of operation. The structure includes: a plurality of dynamic clocked stacks which are configured to receive input data and provide a true logical value and a complement logical value; and a plurality of holding stacks which are configured to provide a hold signal to the dynamic clocked stacks and output the true logical value and the complement logical value in response to the hold signal being activated.