Clock Duty-Cycle Calibration Circuit for Low-Noise Frequency Doubling
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Solution Overview
Problem
Existing clock signal frequency multiplication technologies face challenges in calibrating duty cycle, leading to increased phase noise, power consumption, and circuit complexity, especially when using digital circuits, and high power consumption when using analog circuits.
Innovation Solution
A clock duty cycle calibration and frequency multiplier circuit that separates frequency multiplication and calibration delay units, utilizing a multiplexing module, calibration module, delay module, detection module, control module, and frequency multiplication module to achieve a 50% duty cycle, allowing for low circuit complexity and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an analog circuit is used to implement calibration of a clock signal duty cycle, then the duty cycle calibration precision is improved, but the power consumption increases
Solution Approach 1:
The patent replaces the analog calibration circuit with a digital calibration circuit that uses digital delay elements and logic operations to adjust the duty cycle. This substitution of digital for analog technology achieves duty cycle calibration while significantly reducing power consumption, as digital circuits operate at lower power levels compared to analog circuits requiring continuous voltage adjustment.
Solution Approach 2:
The patent changes the operating parameters by using digital delay control instead of analog voltage control. The duty cycle is calibrated by adjusting digital delay parameters through logic operations rather than continuous analog parameter adjustment, maintaining calibration precision while reducing power consumption through discrete digital control.
2Use of energy by moving object
If a digital circuit is used to implement calibration of a clock signal duty cycle, then the power consumption is reduced, but the phase noise and area increase
Solution Approach 1:
The patent segments the calibration function into multiple independent digital delay elements arranged in series. Each delay element can be independently controlled to adjust the overall delay, allowing precise duty cycle calibration through modular digital components rather than a single complex analog circuit, thereby reducing overall circuit complexity while maintaining functionality.
Solution Approach 2:
The patent designs the digital delay elements and logic circuits to serve multiple functions: duty cycle calibration, phase adjustment, and frequency multiplication preparation. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby reducing overall device complexity while achieving power consumption reduction.
3Productivity
If the duty cycle of the input clock signal deviates from 50%, then the frequency multiplication can be performed, but spurious components appear in the output signal
Solution Approach 1:
The patent applies preliminary duty cycle calibration before the frequency multiplication operation. The digital calibration circuit adjusts the input clock signal duty cycle to exactly 50% using controlled delay elements and logic operations, ensuring that the subsequent frequency multiplication produces clean output signals without spurious components, thereby eliminating harmful factors before they can be generated.
Solution Approach 2:
The patent implements a feedback mechanism where the duty cycle of the clock signal is continuously monitored and adjusted by the digital calibration circuit. The calibration circuit receives feedback about the actual duty cycle and dynamically adjusts the delay parameters to maintain 50% duty cycle, preventing spurious components from appearing in the frequency multiplication output.
Data Source
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AI summary
A clock duty cycle calibration and frequency multiplier circuit used in a square wave frequency multiplier has a multiplexing module (301), which performs a phase-inversion operation on a clock signal according to a control signal; a calibration module (302) which adjusts the duty cycle according to a control signal, and outputs a clock signal with a 50% duty cycle; a delay module (303), which performs a delay operation on the clock signal according to a control signal; a detection module (304), which compares the clock signal and outputs a feedback signal; a control module (305), which outputs a control signal according to the feedback signal; a frequency multiplication module (306), which performs a frequency multiplication operation on the clock signal. Therefore, high-precision clock signal frequency multiplication is implemented with relatively low circuit complexity and low cost.