Read-Once Non-Volatile Memory with Automatic Read Erasure
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Solution Overview
Problem
Existing memory technologies do not effectively address the need for a read-once or destructive readout memory that erases data upon reading, which is crucial for secure storage and non-reversible counter applications.
Innovation Solution
A memory circuit comprising a rewritable non-volatile memory cell with a flip-flop and logic functions that combine the memory cell output with a readout order state, using AND-type logic to ensure data erasure upon reading, and a clock signal to manage the erasing process, allowing for a read-once or volatile memory implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory cell allows multiple read operations, then data can be accessed repeatedly, but data security is compromised for applications requiring one-time access
Solution Approach 1:
The patent applies preliminary action by preparing the memory system with a read counter that tracks the number of read operations before they occur. The counter is initialized to a predetermined value (e.g., 1) and automatically decremented with each read operation, enabling the system to proactively enforce one-time access policies without requiring external intervention or complex security protocols during actual data access.
Solution Approach 2:
The patent introduces a read counter as an intermediary element between the memory cell and the read operation. This counter acts as a mediator that controls whether data can be read by comparing its value against required thresholds. The intermediary mechanism enables flexible data access control by allowing different read permissions (one-time, multiple, or unlimited reads) without modifying the underlying memory cell structure or requiring external security management.
2Reliability
If a memory system implements read-once functionality, then data security is improved, but additional control circuitry increases device complexity
Solution Approach 1:
The patent applies universality by designing a read counter that serves multiple functions: it counts read operations, determines whether read limits have been reached, controls memory access permissions, and can be configured for different read policies (one-time, multiple, or unlimited reads). This multi-functional counter reduces the need for separate control circuits for each function, thereby minimizing overall device complexity while providing robust read-once functionality.
Solution Approach 2:
The patent utilizes parameter changes by configuring the read counter with different initial values and threshold settings to achieve various read access policies. By changing the counter's initial value (e.g., 1 for one-time read, higher values for multiple reads) and comparing against different thresholds, the system can dynamically adjust its security parameters without requiring different hardware circuits for each policy, thus maintaining simplicity while providing flexibility.
3Ease of manufacture
If standard memory cells are used without read erasure, then manufacturing is simpler, but data integrity is compromised for applications requiring automatic data invalidation after reading
Solution Approach 1:
The patent applies self-service by implementing an automatic erasure mechanism that is triggered by the read counter itself. When the counter reaches zero (indicating the maximum number of allowed reads has been reached), it automatically initiates the erasure of the memory cell contents without requiring external control signals or additional management circuits. This self-service approach maintains manufacturing simplicity while ensuring data integrity through automatic invalidation after the permitted read operations.
Solution Approach 2:
The patent implements feedback by using the read counter's state to control the erasure operation. The counter continuously monitors the number of read operations and provides feedback to the erasure control logic. When the counter value reaches the threshold (zero), this feedback signal automatically triggers the erasure sequence, creating a closed-loop system that ensures data integrity without requiring external intervention or complex control circuits.
Data Source
AI summary
A memory includes a rewritable non-volatile memory cell and input circuitry coupled to the memory cell. The input circuitry, in operation, erases the memory cell in response to reception of a request to read the memory cell. Similarly, a read-once memory includes an addressable, non-volatile memory having a plurality of rewriteable memory cells. Input circuitry coupled to the non-volatile memory responds to reception of a request to read content stored at an address in the non-volatile memory by erasing the content stored at the address of the non-volatile memory.