Self-Scheduling Reconfigurable Fabric for Loop Thread Order Control
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Solution Overview
Problem
Existing computing systems face limitations in performance and energy efficiency for compute-intensive tasks such as Fast Fourier Transforms and finite impulse response filters, particularly in applications like synthetic aperture radar, 5G base stations, and machine learning, requiring a more dynamic and configurable architecture.
Innovation Solution
A multi-threaded, coarse-grained configurable computing architecture with self-scheduling and self-reconfiguration capabilities, including a configurable computation circuit, configuration memory, and control circuitry that manages thread execution, data dependencies, and loop access, enabling rapid execution of loop threads and advanced loop execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing computing systems are used for compute-intensive tasks, then basic computation can be performed, but performance and energy efficiency are insufficient
Solution Approach 1:
The patent implements dynamic reconfiguration of the computing fabric, allowing the system to adapt its architecture in real-time based on workload requirements. The configurable circuitry can dynamically change its operational mode and resource allocation to optimize both performance and energy consumption for different compute-intensive tasks.
Solution Approach 2:
The computing system is divided into multiple independent threads that can execute simultaneously on different portions of the configurable fabric. This segmentation allows parallel processing of compute-intensive tasks while enabling selective activation of computational resources, improving both productivity and energy efficiency.
2Adaptability or versatility
If a fixed computing architecture is used, then system simplicity is maintained, but adaptability to different applications is limited
Solution Approach 1:
The patent creates a universal computing fabric that can be configured to perform multiple different functions through software control. The same physical hardware can be reconfigured to execute various algorithms and applications, providing high adaptability without proportionally increasing physical complexity.
Solution Approach 2:
The system incorporates self-scheduling and self-configuration capabilities, where the computing fabric automatically manages its own resource allocation and thread scheduling based on workload characteristics. This reduces the complexity of external control mechanisms while maintaining high adaptability.
3Reliability
If thread execution order is not controlled, then execution flexibility is high, but data dependency correctness cannot be guaranteed
Solution Approach 1:
The patent implements a control mechanism that monitors thread execution and data dependencies, providing feedback to the scheduler. When data dependencies are detected, the system adjusts thread execution order accordingly, ensuring correctness while maintaining flexibility through automated control rather than manual intervention.
Data Source
AI summary
Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.