Asynchronous SAR ADC Delay Tuning for DAC Settling Accuracy
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Solution Overview
Problem
Asynchronous successive approximation analog/digital converters face challenges in determining a suitable delay between comparator decisions, as it must balance providing sufficient time for the digital/analog converter to settle with minimizing the duration of the conversion process, especially for low differential input signals.
Innovation Solution
A method and apparatus for determining a suitable test delay value by converting a digital test value into an analog signal, approximating it bit-by-bit, and evaluating its suitability based on the comparison with the original digital value, with the option to optimize the delay value by testing multiple values and using a time calibration circuit to adjust the delay between comparator decisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a longer delay value is used between comparator decisions, then the digital/analog converter has sufficient time to settle, but the total conversion time increases
Solution Approach 1:
The patent applies dynamics by making the delay value adjustable rather than fixed. The delay circuit can be configured with different delay values depending on the operating conditions, allowing the system to optimize between settling time and conversion speed dynamically. This resolves the contradiction by enabling the delay to be long enough for accurate conversion when needed, but shorter when speed is prioritized.
Solution Approach 2:
The patent changes the parameter of delay value from a static to a variable parameter. By providing multiple delay values and selecting appropriate values based on input signal characteristics and performance requirements, the system can adapt the delay duration to balance settling accuracy and conversion speed, thus resolving the technical contradiction.
2Productivity
If a shorter delay value is used between comparator decisions, then the conversion process is faster, but the digital/analog converter may not have sufficient settling time
Solution Approach 1:
The adjustable delay circuit allows the system to dynamically select appropriate delay values. When high conversion speed is required, a shorter delay can be selected, accepting some trade-off in settling time. When accuracy is prioritized, longer delays can be chosen. This dynamic adjustment resolves the contradiction between speed and accuracy.
Solution Approach 2:
By changing the delay parameter to be variable rather than fixed, the system can optimize conversion speed by selecting shorter delay values when appropriate, while maintaining the capability to use longer delays when accuracy is critical. This parameter flexibility resolves the contradiction between productivity and reliability.
3Measurement precision
If the delay is optimized for low differential input signals, then correct conversion results are obtained, but the conversion duration increases
Solution Approach 1:
The patent addresses this by providing multiple delay values that can be selected based on the input signal characteristics. For low differential input signals requiring higher precision, a longer delay value can be selected to ensure accurate comparator decisions. For other cases, shorter delays can be used to maintain faster conversion, thus resolving the contradiction between measurement precision and time loss.
Data Source
AI summary
A method and an apparatus for determining the suitability of a test delay value between comparator decisions of a comparator circuit of an asynchronous successive approximation analog/digital converter and a method for determining an optimized delay value of a comparator of an asynchronous successive approximation analog/digital converter are provided.